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公开(公告)号：US12057181B2
公开(公告)日：2024-08-06
申请号：US18074556
申请日：2022-12-05
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A shift register circuit, including: a plurality of clock signal lines each supplying a clock pulse respectively; a plurality of cascade-connected register circuits including a top register circuit, and main register circuits providing between the top register circuit and the bottom register circuit; and a forward scan signal line supplying a forward scan signal to the plurality of cascade-connected register circuits.
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公开(公告)号：US10210945B2
公开(公告)日：2019-02-19
申请号：US15848052
申请日：2017-12-20
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US09437143B2
公开(公告)日：2016-09-06
申请号：US14938039
申请日：2015-11-11
Applicant: Japan Display Inc.
Inventor： Takayuki Suzuki , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
Abstract translation: 显示装置包括形成在基板的图像显示区域中的像素电极，形成在图像显示区域中的公共电极，形成在图像显示区域内部的信号线内部，并且电连接到像素电极，形成在外部的外部信号线 图像显示区域，并且电连接到内部信号线，以及形成在图像显示区域内部和外部的公共线，并且电连接到公共电极。 使用在像素电极和公共电极之间产生的电场，在光的控制下显示图像。 在内部信号线和公共电极之间形成耦合电容。 外部信号线各自包括第一部分和比第一部分和内部信号线更高的电阻的第二部分。
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公开(公告)号：US09076403B2
公开(公告)日：2015-07-07
申请号：US14449363
申请日：2014-08-01
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
Abstract translation: 一种包括双向移位寄存器电路的显示装置，包括：多个级联连接的寄存器电路; 各种电路，用于响应于输入到各种终端的各种信号将各种节点设置到各种电压电平; 以及输出电路，其在第一节点的电压为高电平时输出时钟脉冲作为输出脉冲，其中，在正向移位操作时，底部伪寄存器电路未输入复位信号和底部的第一节点 如果底部伪寄存器电路的初始复位电路接收到反向触发信号，则虚拟寄存器电路被复位，并且其中，在反向移位操作时，顶部伪寄存器电路不输入复位信号和顶部伪器件的第一个节点 如果顶部伪寄存器电路的初始复位电路接收到正向触发信号，则寄存器电路复位。
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公开(公告)号：US08902147B2
公开(公告)日：2014-12-02
申请号：US14143655
申请日：2013-12-30
Inventor： Yoshihiro Kotani , Mitsuru Goto
CPC classification number: G09G3/3677 , G11C19/184 , G11C19/28
Abstract: A gate signal line driving circuit and a display device which can suppress the degradation of an element attributed to the use of the element for a long time, and can realize the prolongation of lifetime of the element are provided. With respect to elements to which a HIGH voltage is applied for a long time, a plurality of elements are connected in parallel, and at least some of the plurality of elements are driven by switching elements.
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Patent Agency Ranking
公开(公告)号：US11114177B2
公开(公告)日：2021-09-07
申请号：US16906286
申请日：2020-06-19
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US20180174539A1
公开(公告)日：2018-06-21
申请号：US15898272
申请日：2018-02-16
Applicant: Japan Display Inc.
Inventor： Takayuki SUZUKI , Hiroyuki Abe , Masahiro Maki , Mitsuru Goto
IPC: G09G3/36 , G02F1/1333 , G02F1/1335 , G02F1/1362 , G06F3/041 , G06F3/044 , G02F1/133
CPC classification number: G09G3/3655 , G02F1/13306 , G02F1/133345 , G02F1/13338 , G02F1/133512 , G02F1/133528 , G02F1/136286 , G02F2001/133302 , G02F2201/121 , G02F2201/123 , G02F2202/104 , G06F3/0412 , G06F3/0418 , G06F3/044 , G06F2203/04103 , G09G3/36 , G09G2300/0426 , G09G2320/0219 , G09G2320/0626
Abstract: A display device includes pixel electrodes formed in an image display area of a substrate, a common electrode formed in the image display area, inside signal lines formed inside the image display area, and electrically connected to the pixel electrodes, outside signal lines formed outside the image display area, and electrically connected to the inside signal lines, and a common line formed inside and outside the image display area, and electrically connected to the common electrode. An image is displayed under a control of a light using an electric field developed between the pixel electrodes and the common electrode. A coupling capacitance is formed between the inside signal lines and the common electrode. The outside signal lines each include a first portion, and a second portion higher in electric resistance than the first portion and the inside signal lines.
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公开(公告)号：US09793007B2
公开(公告)日：2017-10-17
申请号：US15090664
申请日：2016-04-05
Applicant: Japan Display Inc.
Inventor： Takahiro Ochiai , Mitsuru Goto , Hiroyuki Higashijima , Yoshihiro Kotani , Shuuichirou Matsumoto
CPC classification number: G11C19/287 , G09G3/3677 , G09G5/003 , G09G2310/0286 , G09G2310/08 , G09G2330/021
Abstract: A bidirectional shift register capable of performing a stable shift operation in both directions and an image display device using the same are provided. In forward shift operation, when reference point N1 is at H level, (n+4)-th unit register circuit as a rear stage of the bidirectional shift register outputs pulse G(n+4) in synchronization with clock pulse V(n+4) inputted to (n+4)-th unit register circuit. A backward direction trigger signal VSTB is generated not only at the time of start of backward shift, but also, for example, in period (time t4 to t5) of one-phase clock immediately after G(n+4) is outputted in vertical blanking interval of the forward shift. The backward direction trigger signal VSTB is inputted to gate of a transistor provided to set reference point N1 of (n+4)-th unit register circuit to H level at the time of start of the backward shift.
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公开(公告)号：US20160307642A1
公开(公告)日：2016-10-20
申请号：US15195000
申请日：2016-06-28
Inventor： Takahiro OCHIAI , Mitsuru Goto , Hiroko Sehata , Hiroyuki Higashijima
CPC classification number: G11C19/28 , G09G3/3674 , G09G3/3677 , G09G3/3688 , G09G2300/0413 , G09G2300/0465 , G09G2310/0283 , G09G2310/0286 , G09G2310/061 , G09G2310/08
Abstract: A display device including a bidirectional shift register circuit, including: a plurality of cascade-connected register circuits; various circuits for setting various nodes to various voltage levels responsive to various signals input to various terminals; and an output circuit which outputs the clock pulse as an output pulse when the voltage of the first node is high level, wherein, at the forward shift operation, the bottom dummy register circuit is not input the reset signal and the first node of the bottom dummy register circuit is reset if the initial reset circuit of the bottom dummy register circuit receives the backward trigger signal, and wherein, at the backward shift operation, the top dummy register circuit is not input the reset signal and the first node of the top dummy register circuit is reset if the initial reset circuit of the top dummy register circuit receives the forward trigger signal.
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公开(公告)号：US20160282660A1
公开(公告)日：2016-09-29
申请号：US15176754
申请日：2016-06-08
Applicant: Japan Display Inc.
Inventor： Takahiro Ochiai , Mitsuru Goto
IPC: G02F1/1345 , H01L27/12 , G02F1/1343 , G02F1/1333 , G02F1/1368
CPC classification number: G02F1/13452 , G02F1/133345 , G02F1/13439 , G02F1/13458 , G02F1/1368 , G02F2001/136254 , H01L24/05 , H01L24/06 , H01L27/124
Abstract: A display device includes a transparent substrate having a display region with a plurality of scanning signal lines and video signal lines intersecting thereon, a first terminal formed outside the display region connecting to a first terminal wiring and a second terminal wiring connected to a semiconductor chip, and an inverted staggered thin film transistor. The first terminal includes a first portion, a second portion on the first portion, a third portion having an exposed planar terminal plate on the second portion, a plurality of first vias between the first portion and the second portion, and a plurality of second vias between the second portion and the third portion. The first portion is connected to the first and second terminal wirings, and each of the plurality of first vias is not overlapped with each of the plurality of second vias in plan view.
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