公开(公告)号：US20210280653A1

公开(公告)日：2021-09-09

申请号：US17191734

申请日：2021-03-04

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI

IPC: H01L27/32

Abstract: The semiconductor device includes a first gate electrode, a first gate insulating film, a semiconductor film, a first electrode, a second electrode, a second gate insulating film, and a second gate electrode. The first gate insulating film is located over the first gate electrode. The semiconductor film is located over the first gate insulating film and overlaps with the first gate electrode. The first electrode and the second electrode are each located over and in contact with the semiconductor film. The second gate insulating film is located over the first electrode and the second electrode. The second gate electrode is located over the second gate insulating film and overlaps with the second electrode and the first gate electrode. The first electrode is completely exposed from the second gate electrode.

公开(公告)号：US20170315413A1

公开(公告)日：2017-11-02

申请号：US15651220

申请日：2017-07-17

Applicant: Japan Display Inc.

Inventor： Hidetatsu NAKAMURA ,  Osamu ITOU ,  Takeshi SAKAI

IPC: G02F1/1343 ,  G02F1/1362

CPC classification number: G02F1/134363 ,  G02F1/136286 ,  G02F2001/134372

Abstract: A pixel electrode is configured of one comb tooth portion and a contact portion whose width is widened from the end portion of the comb tooth portion in a first direction that is the extending direction of a scanning line. The width of the contact portion is not expanded in a direction opposite to the first direction, and the production of a domain is prevented. A picture signal line is bent in the direction in which the width of the contact portion of the pixel electrode is widened, so that the comb tooth portion of the pixel electrode can be disposed in the center between the picture signal lines, and the width of the contact portion can be formed in a sufficient width in the direction in which the picture signal line is bent. Thus, the contact margin of the pixel electrode can be provided.

公开(公告)号：US20150346566A1

公开(公告)日：2015-12-03

申请号：US14723577

申请日：2015-05-28

Applicant: Japan Display Inc.

Inventor： Hidetatsu NAKAMURA ,  Osamu ITOU ,  Takeshi SAKAI

IPC: G02F1/1343 ,  G02F1/1333

CPC classification number: G02F1/134363 ,  G02F1/136286 ,  G02F2001/134372

Abstract: A pixel electrode is configured of one comb tooth portion and a contact portion whose width is widened from the end portion of the comb tooth portion in a first direction that is the extending direction of a scanning line. The width of the contact portion is not expanded in a direction opposite to the first direction, and the production of a domain is prevented. A picture signal line is bent in the direction in which the width of the contact portion of the pixel electrode is widened, so that the comb tooth portion of the pixel electrode can be disposed in the center between the picture signal lines, and the width of the contact portion can be formed in a sufficient width in the direction in which the picture signal line is bent. Thus, the contact margin of the pixel electrode can be provided.

Abstract translation: 像素电极由沿着作为扫描线的延伸方向的第一方向从梳齿部的端部宽度变宽的一个梳齿部和接触部构成。 接触部分的宽度不会沿与第一方向相反的方向膨胀，并且防止了区域的产生。 图像信号线在像素电极的接触部分的宽度被加宽的方向上弯曲，使得像素电极的梳齿部分可以设置在图像信号线之间的中心，并且宽度 接触部分可以沿图像信号线弯曲的方向形成足够的宽度。 因此，可以提供像素电极的接触余量。

公开(公告)号：US20150055043A1

公开(公告)日：2015-02-26

申请号：US14458314

申请日：2014-08-13

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Toshimasa ISHIGAKI ,  Yasushi TOMIOKA

IPC: G02F1/1343 ,  G02F1/1362 ,  G02F1/1337 ,  G02F1/1333

CPC classification number: G02F1/134363 ,  G02F1/133345 ,  G02F1/136227 ,  G02F2001/134372

Abstract: In an IPS mode liquid crystal display device, a counter electrode is formed flat on a first insulating film. A second insulating film is formed in the peripheral portion of the counter electrode. A third insulating film is formed so as to cover the counter electrode and the second insulating film. A pixel electrode is formed on the third insulating film. The second and third insulating films are present between the pixel electrode and the counter electrode in the periphery of the pixel. The third insulating film is present between the pixel electrode and the counter electrode in the portion other than the peripheral portion of the pixel. An electric field between the pixel electrode and the counter electrode is smaller in the periphery of the pixel than in the vicinity of the center of the pixel, to prevent the occurrence of a domain in the periphery of the pixel.

Abstract translation: 在IPS模式的液晶显示装置中，对置电极在第一绝缘膜上平坦地形成。 第二绝缘膜形成在对电极的周边部分中。 形成第三绝缘膜以覆盖对电极和第二绝缘膜。 像素电极形成在第三绝缘膜上。 第二和第三绝缘膜存在于像素周边的像素电极和对电极之间。 第三绝缘膜存在于像素电极和对置电极之间的除了像素的周边部分之外的部分中。 像素电极和对电极之间的电场在像素的周边比在像素的中心附近更小，以防止在像素的周围出现域。

公开(公告)号：US20240194795A1

公开(公告)日：2024-06-13

申请号：US18438564

申请日：2024-02-12

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Yuichiro HANYU ,  Masahiro WATABE

IPC: H01L29/786 ,  G02F1/1343 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L27/12 ,  H01L29/423 ,  H10K59/121

CPC classification number: H01L29/78696 ,  H01L21/02164 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/7869 ,  G02F1/134363 ,  G02F1/1368 ,  G02F1/13685 ,  H10K59/1213

Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

公开(公告)号：US20230292551A1

公开(公告)日：2023-09-14

申请号：US18176503

申请日：2023-03-01

Applicant: Japan Display Inc.

Inventor： Masashi TSUBUKU ,  Takeshi SAKAI ,  Kentaro MIURA ,  Hajime WATAKABE ,  Takaya TAMARU ,  Hiroshi TABATAKE ,  Yutaka UMEDA

IPC: H10K59/121

CPC classification number: H10K59/1213 ,  H01L27/1255

Abstract: A display device includes a light-emitting element; a first transistor and a second transistor connected in series between the light-emitting element and a driving power line; a third transistor electrically connected to a gate electrode of the first transistor; and a fourth transistor connected in parallel between a drain electrode of the first transistor and the light-emitting element, wherein a ratio of a channel width W1 to a channel length L1 of the first transistor (a W1/L1 ratio) and a ratio of a channel width W2 to a channel length L2 of the second transistor (a W2/L2 ratio) are larger than a ratio of a channel width W3 to a channel length L3 of the third transistor (a W3/L3 ratio) and a ratio of a channel width W4 to a channel length L4 of the fourth transistor (a W4/L4 ratio).

公开(公告)号：US20230007861A1

公开(公告)日：2023-01-12

申请号：US17859004

申请日：2022-07-07

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Hajime WATAKABE ,  Akihiro HANADA

IPC: H01L29/786 ,  H01L27/12

Abstract: According to one embodiment, a semiconductor device includes a first transistor which includes a an oxide semiconductor layer, and a second transistor connected to first and a second gate electrodes of the first transistor, wherein the oxide semiconductor layer is provided between the first and second gate electrodes in a cross-sectional view, the oxide semiconductor layer includes a first channel formation region overlapping the second gate electrode and a second channel formation region not overlapping the second gate electrode in a plan view, and a resistance value between the second gate electrode and the second transistor is higher than a resistance value between the first gate electrode and the second transistor.

公开(公告)号：US20220231149A1

公开(公告)日：2022-07-21

申请号：US17575635

申请日：2022-01-14

Applicant: Japan Display Inc.

Inventor： Akihiro HANADA ,  Kentaro MIURA ,  Hajime WATAKABE ,  Masashi TSUBUKU ,  Toshinari SASAKI ,  Takaya TAMARU ,  Takeshi SAKAI

IPC: H01L29/66 ,  H01L21/02 ,  H01L29/40 ,  H01L21/3115

Abstract: According to one embodiment, a method of manufacturing a semiconductor device comprises forming an oxide semiconductor layer, forming a gate insulating layer in contact with the oxide semiconductor layer and covering the oxide semiconductor layer, and forming a gate electrode on the gate insulating layer so as to overlap the oxide semiconductor layer, and injecting boron through the gate electrode and the gate insulating layer after forming the gate electrode, wherein a boron concentration included in a region of the gate insulating layer overlapping the gate electrode is in a range of 1E+16 [atoms/cm3] or more.

公开(公告)号：US20210367082A1

公开(公告)日：2021-11-25

申请号：US17393452

申请日：2021-08-04

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Yuichiro HANYU ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L29/423

Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

公开(公告)号：US20210280614A1

公开(公告)日：2021-09-09

申请号：US17191725

申请日：2021-03-04

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI

IPC: H01L27/12

Abstract: The semiconductor device comprises a gate electrode, a first gate insulating film overlapping a part of the side surface and the upper surface of the gate electrode, a second gate insulating film overlapping the upper surface of the gate electrode, a semiconductor film provided on the upper surface of the second gate insulating film and overlapping the gate electrode and a first terminal and a second terminal overlapping the upper surface of the semiconductor film. In a plan view, a first region is a region where the semiconductor film overlaps the upper surface of the first gate insulating film and the second gate insulating film between the first terminal and the second terminal, and a third region is a region that overlaps both a part of the upper surface of the gate electrode and the second gate insulating film and does not overlap the first gate insulating film.