公开(公告)号：US20200227563A1

公开(公告)日：2020-07-16

申请号：US16735800

申请日：2020-01-07

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  Yuichiro HANYU ,  Hiroki HIDAKA

IPC: H01L29/786 ,  H01L29/423 ,  H01L21/02 ,  H01L27/12

Abstract: A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view.

公开(公告)号：US20170358610A1

公开(公告)日：2017-12-14

申请号：US15620997

申请日：2017-06-13

Applicant: Japan Display Inc.

Inventor： Yuichiro HANYU ,  Hirokazu WATANABE

IPC: H01L27/12

CPC classification number: H01L27/1225 ,  H01L27/1229 ,  H01L27/1233 ,  H01L27/1251 ,  H01L29/7869 ,  H01L51/0529

Abstract: According to one embodiment, a semiconductor device includes a first insulating film, a first semiconductor layer formed of polycrystalline silicon, a second semiconductor layer formed of an oxide semiconductor, a second insulating film, a first gate electrode, a second gate electrode, a third insulating film formed of silicon nitride, and a protection layer. The protection layer is located between the second insulating film and the third insulating film, is opposed to the second semiconductor layer, and is formed of either an aluminum oxide or fluorinated silicon nitride.

公开(公告)号：US20230387319A1

公开(公告)日：2023-11-30

申请号：US18447400

申请日：2023-08-10

Applicant: Japan Display Inc.

Inventor： Yohei YAMAGUCHI ,  Yuichiro HANYU ,  Hiroki HIDAKA

IPC: H01L29/786 ,  H01L21/02 ,  H01L29/423 ,  H01L27/12 ,  H10K59/126

CPC classification number: H01L29/7869 ,  H01L21/02554 ,  H01L21/02266 ,  H01L29/42384 ,  H01L29/78696 ,  H01L27/1251 ,  H01L29/78648 ,  H01L27/124 ,  H01L27/1225 ,  H10K59/126

Abstract: A semiconductor device including a first oxide semiconductor layer, a first gate electrode opposing the first oxide semiconductor layer, a first gate insulating layer between the first oxide semiconductor layer and the first gate electrode, a first insulating layer covering the first oxide semiconductor layer and having a first opening, a first conductive layer above the first insulating layer and in the first opening, the first conductive layer being electrically connected to the first oxide semiconductor layer, and an oxide layer between an upper surface of the first insulating layer and the first conductive layer, wherein the first insulating layer is exposed from the oxide layer in a region not overlapping the first conductive layer in a plan view.

公开(公告)号：US20200227569A1

公开(公告)日：2020-07-16

申请号：US16831958

申请日：2020-03-27

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Yuichiro HANYU ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L29/423

Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

公开(公告)号：US20240194795A1

公开(公告)日：2024-06-13

申请号：US18438564

申请日：2024-02-12

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Yuichiro HANYU ,  Masahiro WATABE

IPC: H01L29/786 ,  G02F1/1343 ,  G02F1/1368 ,  H01L21/02 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L27/12 ,  H01L29/423 ,  H10K59/121

CPC classification number: H01L29/78696 ,  H01L21/02164 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L27/1225 ,  H01L27/124 ,  H01L27/1262 ,  H01L27/127 ,  H01L29/42384 ,  H01L29/7869 ,  G02F1/134363 ,  G02F1/1368 ,  G02F1/13685 ,  H10K59/1213

Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

公开(公告)号：US20210367082A1

公开(公告)日：2021-11-25

申请号：US17393452

申请日：2021-08-04

Applicant: Japan Display Inc.

Inventor： Takeshi SAKAI ,  Yuichiro HANYU ,  Masahiro WATABE

IPC: H01L29/786 ,  H01L27/12 ,  H01L21/02 ,  H01L21/383 ,  H01L21/385 ,  H01L21/428 ,  H01L29/423

Abstract: The purpose of the invention is to form the TFT of the oxide semiconductor, in which influence of variation in mask alignment is suppressed, thus, manufacturing a display device having a TFT of stable characteristics. The concrete measure is as follows. A display device including plural pixels, each of the plural pixels having a thin film transistor (TFT) of an oxide semiconductor comprising: a width of the oxide semiconductor in the channel width direction is wider than a width of the gate electrode in the channel width direction.

公开(公告)号：US20180331128A1

公开(公告)日：2018-11-15

申请号：US16041259

申请日：2018-07-20

Applicant: Japan Display Inc.

Inventor： Yuichiro HANYU ,  Hirokazu WATANABE

IPC: H01L27/12 ,  H01L29/786 ,  H01L51/05

Abstract: According to one embodiment, a semiconductor device includes a first insulating film, a first semiconductor layer formed of polycrystalline silicon, a second semiconductor layer formed of an oxide semiconductor, a second insulating film, a first gate electrode, a second gate electrode, a third insulating film formed of silicon nitride, and a protection layer. The protection layer is located between the second insulating film and the third insulating film, is opposed to the second semiconductor layer, and is formed of either an aluminum oxide or fluorinated silicon nitride.