利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

65 条记录 (耗时 0.031 秒)

    PHASE LINEARITY TEST CIRCUIT
    14.
    发明申请
    PHASE LINEARITY TEST CIRCUIT 有权
    相位线性测试电路

    公开(公告)号：US20070252735A1

    公开(公告)日：2007-11-01

    申请号：US11414751

    申请日：2006-04-28

    申请人： Xudong Shi ,  Fariborz Assaderaghi

    发明人： Xudong Shi ,  Fariborz Assaderaghi

    IPC分类号： H03M1/06

    CPC分类号： G01R31/31727

    摘要： A circuit includes a phase interpolator and a self test circuit. The phase interpolator is to provide a interpolator output having a phase corresponding to a respective phase step in a plurality of phase steps. The interpolator output is a weighted combination of one or more of a plurality of phasor signals. The self test circuit includes a phase detector coupled to a reference signal and the interpolator output, a phase-difference-to-voltage converter coupled to the phase detector, an analog-to-digital converter (ADC) coupled to the phase-difference-to-voltage converter, and control logic. The phase detector is to generate an output that is proportional to a phase difference between the reference signal and the interpolator output. The phase-difference-to-voltage converter is to convert the output from the phase detector into a corresponding voltage. The ADC is to convert an output from the phase-difference-to-voltage converter into a corresponding digital value. The control logic is to test the phase interpolator using the self-test circuit.

    摘要翻译： 电路包括相位内插器和自检电路。 相位插值器是提供具有对应于多个相位步骤中的相位相位阶段的相位的内插器输出。 内插器输出是多个相量信号中的一个或多个的加权组合。 自检电路包括耦合到参考信号和内插器输出的相位检测器，耦合到相位检测器的相位差电压转换器，耦合到相位差转换器的模 - 数转换器（ADC） 电压转换器和控制逻辑。 相位检测器将产生与参考信号和内插器输出之间的相位差成比例的输出。 相位差电压转换器将相位检测器的输出转换成相应的电压。 ADC将将相位差电压转换器的输出转换为相应的数字值。 控制逻辑是使用自检电路测试相位插值器。

    Soi-body selective link method and apparatus
    16.
    发明授权
    Soi-body selective link method and apparatus 失效
    单体选择性联动方法及装置

    公开(公告)号：US06410369B1

    公开(公告)日：2002-06-25

    申请号：US09591511

    申请日：2000-06-12

    申请人： Roy Childs Flaker ,  Louis L. Hsu ,  Fariborz Assaderaghi ,  Jack A. Mandelman

    发明人： Roy Childs Flaker ,  Louis L. Hsu ,  Fariborz Assaderaghi ,  Jack A. Mandelman

    IPC分类号： H01L2100

    CPC分类号： H01L27/1104 ,  H01L27/1203

    摘要： A silicon-on-insulator (SOI) structure and method of making the same includes an SOI wafer having a silicon layer of an original thickness dimension formed upon an isolation oxidation layer. At least two p-type bodies of at least two SOI field effect transistors (PFETs) are formed in the silicon layer. At least two n-type bodies of at least two SOI field effect transistors (NFETs) are also formed in the silicon layer. Lastly, an SOI body link is formed in the silicon layer of the SOI wafer adjacent the isolation oxidation layer for selectively connecting desired bodies of either the p-type SOI FETs or the n-type SOI FETs and for allowing the connected bodies to float.

    摘要翻译： 绝缘体上硅（SOI）结构及其制造方法包括具有形成在隔离氧化层上的原始厚度尺寸的硅层的SOI晶片。 在硅层中形成至少两个至少两个SOI场效应晶体管（PFET）的p型体。 在硅层中还形成至少两个至少两个SOI场效应晶体管（NFET）的n型体。 最后，在隔离氧化层附近的SOI晶片的硅层中形成SOI本体连接，用于选择性地连接p型SOI FET或n型SOI FET的所需体，并允许连接体浮置。

    Large value capacitor for SOI
    19.
    发明授权
    Large value capacitor for SOI 失效
    SOI的大值电容器

    公开(公告)号：US5770875A

    公开(公告)日：1998-06-23

    申请号：US724287

    申请日：1996-09-16

    申请人： Fariborz Assaderaghi ,  Louis L. Hsu ,  Jack A. Mandelman ,  William R. Tonti

    发明人： Fariborz Assaderaghi ,  Louis L. Hsu ,  Jack A. Mandelman ,  William R. Tonti

    IPC分类号： H01L21/334 ,  H01L21/84 ,  H01L29/786 ,  H01L21/8242 ,  H01L27/108

    CPC分类号： H01L29/66181 ,  H01L21/84

    摘要： Large capacitance, low-impedance decoupling capacitors in SOI and their method of fabrication. A high conductivity trench substrate contact is made adjacent to the capacitor by removal of insulator lining the capacitor by use of an extra mask thereby making a substrate contact when the trench is filled with doped polysilicon. The inventive process is compatible with and easily integrated into existing SOI logic technologies. The SOI decoupling capacitors are formed in trenches which pass through the silicon and buried oxide layers and into the underlying silicon substrate.

    摘要翻译： SOI中的大电容，低阻抗去耦电容及其制造方法。 通过使用额外的掩模去除夹在电容器上的绝缘体，使与电容器相邻的高导电性沟槽衬底接触，从而当沟槽填充有掺杂多晶硅时进行衬底接触。 本发明的方法与现有的SOI逻辑技术兼容并容易地集成。 SOI去耦电容器形成在通过硅和掩埋氧化物层并进入下面的硅衬底的沟槽中。

    Drift cancellation technique for use in clock-forwarding architectures
    20.
    发明授权
    Drift cancellation technique for use in clock-forwarding architectures 有权

    公开(公告)号：US08325861B2

    公开(公告)日：2012-12-04

    申请号：US13341612

    申请日：2011-12-30

    申请人： Kun-Yung Chang ,  Fariborz Assaderaghi

    发明人： Kun-Yung Chang ,  Fariborz Assaderaghi

    IPC分类号： H04L25/08

    CPC分类号： H03L7/00 ,  H03L7/06

    摘要： A circuit includes a frequency synthesizer, N phase mixers coupled to the frequency synthesizer, a plurality of receivers, and a calibration circuit. The frequency synthesizer is to receive a reference clock signal and is to output a primary clock signal. A respective phase mixer in the N phase mixers is to output a respective secondary clock signal having a corresponding phase. A respective receiver in the plurality of receivers is coupled to two of the N phase mixers, and at a respective time is to receive data in accordance with the respective secondary clock signal from one of the two phase mixers coupled to the respective receiver. The calibration circuit is to calibrate a secondary clock signal output by a respective phase mixer in the N phase mixers by adjusting the phase of the secondary clock signal of the respective phase mixer.