公开(公告)号：US08525169B1

公开(公告)日：2013-09-03

申请号：US13572289

申请日：2012-08-10

申请人： Daniel C. Edelstein ,  Stephen M. Gates ,  Edward W. Kiewra ,  Satyanarayana V. Nitta ,  Ramachandran Muralidhar ,  Dirk Pfeiffer

发明人： Daniel C. Edelstein ,  Stephen M. Gates ,  Edward W. Kiewra ,  Satyanarayana V. Nitta ,  Ramachandran Muralidhar ,  Dirk Pfeiffer

IPC分类号： H01L21/66 ,  H01L21/74

CPC分类号： H01L23/544 ,  H01L21/268 ,  H01L21/76894 ,  H01L22/14 ,  H01L23/5226 ,  H01L23/53271 ,  H01L23/573 ,  H01L2223/5444 ,  H01L2223/5448 ,  H01L2924/0002 ,  H04L9/3247 ,  H04L9/3278 ,  H01L2924/00

摘要： The present disclosure relates to a secure device having a physical unclonable function. The device includes an integrated circuit having a semiconducting material in at least one via in a backend of the integrated circuit. The present disclosure also relates to a method for manufacturing a secure device having a physical unclonable function. The method includes providing an integrated circuit and adding a semiconducting material to at least one via in a backend of the integrated circuit. In some instances a property of the semiconducting material in the at least one via is measured to derive a signature.

摘要翻译： 本公开涉及具有物理不可克隆功能的安全装置。 该器件包括在集成电路的后端中的至少一个通孔中具有半导体材料的集成电路。 本公开还涉及一种用于制造具有物理不可克隆功能的安全装置的方法。 该方法包括提供集成电路并将集成电路的后端中的至少一个通孔添加半导体材料。 在一些情况下，测量至少一个通孔中的半导体材料的特性以导出签名。

公开(公告)号：US20120132913A1

公开(公告)日：2012-05-31

申请号：US12955203

申请日：2010-11-29

申请人： Kuen-Ting Shiu ,  Dechao Guo ,  Shu-Jen Han ,  Edward W. Kiewra ,  Masaharu Kobayashi

发明人： Kuen-Ting Shiu ,  Dechao Guo ,  Shu-Jen Han ,  Edward W. Kiewra ,  Masaharu Kobayashi

IPC分类号： H01L29/78 ,  H01L21/20

CPC分类号： H01L29/0603 ,  H01L21/28158 ,  H01L21/28264 ,  H01L29/517 ,  H01L29/66522 ,  H01L29/78 ,  H01L29/7833

摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.

摘要翻译： 本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度 单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

公开(公告)号：US07287325B2

公开(公告)日：2007-10-30

申请号：US10908392

申请日：2005-05-10

申请人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

发明人： Kaushik Chanda ,  James J. Demarest ,  Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Ping-Chuan Wang ,  Yun-Yu Wang

IPC分类号： H01K3/10

CPC分类号： B24B37/042 ,  H01L21/31144 ,  H01L21/76834 ,  H01L21/7684 ,  H01L21/76849 ,  H01L21/76852 ,  H01L21/76885 ,  Y10T29/49156 ,  Y10T29/49165 ,  Y10T29/49204

摘要： Disclosed are a damascene and dual damascene processes both of which incorporate the use of a release layer to remove trace amounts of residual material between metal interconnect lines. The release layer is deposited onto a dielectric layer. The release layer comprises an organic material, a dielectric material, a metal or a metal nitride. Trenches are etched into the dielectric layer. The trenches are lined with a liner and filled with a conductor. The conductor and liner materials are polished off the release layer. However, trace amounts of the residual material may remain. The release layer is removed (e.g., by an appropriate solvent or wet etching process) to remove the residual material. If the trench is formed such that the release layer overlaps the walls of the trench, then when the release layer is removed another dielectric layer can be deposited that reinforces the corners around the top of the metal interconnect line.

摘要翻译： 公开了一种镶嵌和双镶嵌工艺，其中两者都结合使用剥离层以在金属互连线之间移除痕量的残余材料。 释放层沉积在电介质层上。 释放层包括有机材料，电介质材料，金属或金属氮化物。 沟槽蚀刻到电介质层中。 沟槽内衬衬里，填充导体。 导体和衬里材料从剥离层抛光。 然而，痕量的剩余材料可能会残留。 去除脱模层（例如，通过适当的溶剂或湿蚀刻工艺）以除去残留的材料。 如果沟槽形成为使得剥离层与沟槽的壁重叠，则当除去剥离层时，可以沉积另外的介电层，加强围绕金属互连线的顶部的拐角。

公开(公告)号：US06486526B1

公开(公告)日：2002-11-26

申请号：US09223826

申请日：1999-01-04

申请人： Chandrasekhar Narayan ,  Edward W. Kiewra ,  Carl J. Radens ,  Axel C. Brintzinger

发明人： Chandrasekhar Narayan ,  Edward W. Kiewra ,  Carl J. Radens ,  Axel C. Brintzinger

IPC分类号： H01L2900

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： A fuse structure in an integrated circuit chip is described that includes an insulated semiconductor substrate; a fuse bank integral to the insulated semiconductor substrate consisting of a plurality of parallel co-planar fuse links; and voids interspersed between each pair of the fuse links, the voids extending beyond a plane defined by the co-planar fuse links. The voids surrounding the spot to be hit by a laser beam during fuse blow operation act as a crack stop to prevent damage to adjacent circuit elements or other fuse links present. By suitably shaping and positioning the voids, a tighter pitch between fuses may be obtained.

摘要翻译： 描述了集成电路芯片中的熔丝结构，其包括绝缘半导体衬底; 一个与多个并联的共面熔断体组成的绝缘半导体衬底整体的保险丝组; 并且散布在每对熔丝链之间的空隙，空隙延伸超过由共面熔丝链限定的平面。 在保险丝熔断操作期间，由激光束击中的点周围的空隙作为裂纹停止，以防止对存在的相邻电路元件或其它熔断体的损坏。 通过适当地定形和定位空隙，可以获得保险丝之间更紧密的间距。

公开(公告)号：US06383920B1

公开(公告)日：2002-05-07

申请号：US09757894

申请日：2001-01-10

申请人： Ping-Chuan Wang ,  Ronald G. Filippi ,  Robert D. Edwards ,  Edward W. Kiewra ,  Roy C. Iggulden

发明人： Ping-Chuan Wang ,  Ronald G. Filippi ,  Robert D. Edwards ,  Edward W. Kiewra ,  Roy C. Iggulden

IPC分类号： H01L214763

CPC分类号： H01L21/76847 ,  H01L21/76807 ,  H01L21/76811 ,  H01L21/76813 ,  H01L21/76843 ,  H01L23/5226 ,  H01L2924/0002 ,  H01L2924/00

摘要： The present invention relates generally to a method of enclosing a via in a dual damascene process. In one embodiment of the disclosed method, the via is etched first and a first barrier metal or liner is deposited in the via, the trench is then etched and a second barrier metal or liner is deposited in the trench, and finally the via and trench are filled or metallized in a dual damascene process, thereby forming a via or interconnect and a line. Alternatively, the trench may be etched first and a first barrier metal or liner deposited in the trench, then the via is etched and a second barrier metal or liner is deposited in the via, and finally the trench and via are filled or metallized in a dual damascene process. The barrier metal or liner encloses the via, thereby reducing void formation due to electromigration.

摘要翻译： 本发明一般涉及在双镶嵌工艺中封闭通孔的方法。 在所公开的方法的一个实施例中，首先蚀刻通孔，并且在通孔中沉积第一阻挡金属或衬垫，然后蚀刻沟槽，并且在沟槽中沉积第二阻挡金属或衬垫，最后沉积通孔和沟槽 在双镶嵌工艺中填充或金属化，从而形成通孔或互连线。 或者，可以首先蚀刻沟槽并且沉积在沟槽中的第一阻挡金属或衬垫，然后蚀刻通孔，并且在通孔中沉积第二阻挡金属或衬垫，最后将沟槽和通孔填充或金属化在 双镶嵌工艺。 阻挡金属或衬里封闭通孔，从而减少由于电迁移而导致的空隙形成。

公开(公告)号：US07674675B2

公开(公告)日：2010-03-09

申请号：US11485599

申请日：2006-07-12

申请人： Zachary E. Berndlmaier ,  Edward W. Kiewra ,  Carl J. Radens ,  William R. Tonti

发明人： Zachary E. Berndlmaier ,  Edward W. Kiewra ,  Carl J. Radens ,  William R. Tonti

IPC分类号： H01L21/8242

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

摘要翻译： 本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物， 具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。

公开(公告)号：US20120261718A1

公开(公告)日：2012-10-18

申请号：US13085511

申请日：2011-04-13

申请人： Norma E. Sosa Cortes ,  Edward W. Kiewra ,  Masaharu Kobayashi ,  Kuen-Ting Shiu

发明人： Norma E. Sosa Cortes ,  Edward W. Kiewra ,  Masaharu Kobayashi ,  Kuen-Ting Shiu

IPC分类号： H01L29/78 ,  H01L21/336

CPC分类号： H01L29/66522 ,  H01L29/41783 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7838 ,  H01L29/7848

摘要： The present disclosure provides a buried channel semiconductor structure in which a crystallographic wet etch is used to tailor the profile of etched regions formed into a multilayered substrate which includes a compound semiconductor layer located atop a buried semiconductor channel material layer. The use of crystallographic wet etching on a compound semiconductor allows one to tailor the shape of a source recess region and a drain recess region formed into a multilayered substrate. This allows for the control of gate overlap/underlap. Also, the use of crystallographic wet etching on a compound semiconductor allows independent control of the length of an underlying buried semiconductor channel region.

摘要翻译： 本公开提供了掩埋沟道半导体结构，其中使用结晶湿蚀刻来定制形成多层衬底的蚀刻区域的轮廓，其包括位于掩埋半导体沟道材料层顶部的化合物半导体层。 在化合物半导体上使用结晶湿式蚀刻可以使形成多层基板的源极凹部区域和漏极凹陷区域的形状成为可能。 这允许控制栅极重叠/欠压。 此外，在化合物半导体上使用晶体湿式蚀刻可以独立控制下面的掩埋半导体沟道区的长度。

公开(公告)号：US07361584B2

公开(公告)日：2008-04-22

申请号：US10904329

申请日：2004-11-04

申请人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

发明人： Ronald G. Filippi ,  Roy C. Iggulden ,  Edward W. Kiewra ,  Stephen K. Loh ,  Ping-Chuan Wang

IPC分类号： H01L21/4763

CPC分类号： H01L21/7684 ,  H01L21/3212 ,  H01L21/7688 ,  H01L22/24 ,  H01L23/53238 ,  H01L2924/0002 ,  H01L2924/00

摘要： A method and structure for the detection of residual liner materials after polishing in a damascene processes includes an integrated circuit comprising a substrate; a dielectric layer over the substrate; a marker layer over the dielectric layer; a liner over the marker layer and dielectric layer; and a metal layer over the liner, wherein the marker layer comprises ultraviolet detectable material, which upon excitation by an ultraviolet ray signals an absence of the metal layer and the liner over the marker layer. Moreover, the marker layer comprises a separate layer from the dielectric layer. Additionally, the ultraviolet detectable material comprises fluorescent material or phosphorescent material.

摘要翻译： 用于在镶嵌工艺中抛光之后检测残留衬垫材料的方法和结构包括：包括衬底的集成电路; 介电层; 电介质层上的标记层; 标记层和电介质层上的衬垫; 以及在所述衬里上的金属层，其中所述标记层包括紫外线可检测材料，其在通过紫外线激发时表示在所述标记层上不存在所述金属层和所述衬垫。 此外，标记层包括与电介质层分离的层。 另外，紫外线可检测材料包括荧光材料或磷光材料。

公开(公告)号：US07102204B2

公开(公告)日：2006-09-05

申请号：US10710256

申请日：2004-06-29

申请人： Zachary E. Berndlmaier ,  Edward W. Kiewra ,  Carl J. Radens ,  William R. Tonti

发明人： Zachary E. Berndlmaier ,  Edward W. Kiewra ,  Carl J. Radens ,  William R. Tonti

IPC分类号： H01L29/00

CPC分类号： H01L29/66181 ,  H01L21/84 ,  H01L27/0629 ,  H01L27/0805 ,  H01L27/1087 ,  H01L27/1203

摘要： The invention provides a fingered decoupling capacitor in the bulk silicon region that are formed by etching a series of minimum or sub-minimum trenches in the bulk silicon region, oxidizing these trenches, removing the oxide from at least one or more disjoint trenches, filling all the trenches with either in-situ doped polysilicon, intrinsic polysilicon that is later doped through ion implantation, or filling with a metal stud, such as tungsten and forming standard interconnects to the capacitor plates.

摘要翻译： 本发明提供了一种在本体硅区域中的指状去耦电容器，其通过在本体硅区域中蚀刻一系列最小或次最小沟槽而形成，氧化这些沟槽，从至少一个或多个不相交的沟槽中去除氧化物， 具有原位掺杂多晶硅的沟槽，后来通过离子注入掺杂的本征多晶硅，或者用金属柱（例如钨）填充并形成标准互连到电容器板。

公开(公告)号：US06566238B2

公开(公告)日：2003-05-20

申请号：US09860570

申请日：2001-05-21

申请人： Axel C. Brintzinger ,  Edward W. Kiewra ,  Chandrasekhar Narayan ,  Carl J. Radens

发明人： Axel C. Brintzinger ,  Edward W. Kiewra ,  Chandrasekhar Narayan ,  Carl J. Radens

IPC分类号： H01L2144

CPC分类号： H01L23/5258 ,  H01L2924/0002 ,  H01L2924/3011 ,  H01L2924/00

摘要： An integrated circuit has primary devices and redundant devices being selective substituted for the primary devices through at least one fuse. The fuse includes a first layer having at least one fuse link region, a second layer over the first layer and cavities in the second layer above the fuse link region.

摘要翻译： 集成电路具有初级器件，并且冗余器件通过至少一个熔丝被选择性地代替初级器件。 熔丝包括具有至少一个熔丝链接区域的第一层，第一层上的第二层和熔丝链接区域上方的第二层中的空腔。