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29 条记录 (耗时 0.034 秒)

    Stacked and tunable power fuse
    11.
    发明授权
    Stacked and tunable power fuse 有权
    堆叠和可调电源保险丝

    公开(公告)号：US08598679B2

    公开(公告)日：2013-12-03

    申请号：US12956025

    申请日：2010-11-30

    申请人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    发明人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    IPC分类号： H01L23/52

    CPC分类号： H01L27/0288 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

    摘要翻译： 本公开提供了一种半导体器件，其包括晶体管，其包括衬底，源极，漏极和栅极以及堆叠在晶体管上的熔丝。 保险丝包括耦合到晶体管的漏极的阳极触点，阴极触点和分别经由第一肖特基二极管和第二肖特基二极管耦合到阴极触点和阳极触点的电阻器。 还提供了一种制造这种半导体器件的方法。

    High voltage resistor with biased-well
    13.
    发明授权
    High voltage resistor with biased-well 有权
    具有偏压井的高压电阻

    公开(公告)号：US08786050B2

    公开(公告)日：2014-07-22

    申请号：US13100714

    申请日：2011-05-04

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L21/02

    CPC分类号： H01L28/20 ,  H01L27/0207 ,  H01L27/0802

    摘要： Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

    摘要翻译： 提供高压半导体器件。 半导体器件包括位于衬底中的相对掺杂的掺杂阱。 半导体器件包括位于掺杂阱上的电介质结构。 邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。 半导体器件包括位于电介质结构上的细长多晶硅结构。 细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离 细长多晶硅结构。 预定距离在从大约0 * L到大约0.1 * L的范围内。

    Source tip optimization for high voltage transistor devices
    14.
    发明授权
    Source tip optimization for high voltage transistor devices 有权
    高压晶体管器件的源尖优化

    公开(公告)号：US08629026B2

    公开(公告)日：2014-01-14

    申请号：US12944959

    申请日：2010-11-12

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L21/22 ,  H01L21/331 ,  H01L21/336 ,  H01L21/38 ,  H01L21/425

    CPC分类号： H01L29/7816 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835

    摘要： The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

    摘要翻译： 本公开提供了一种用于制造高压半导体器件的方法。 该方法包括在衬底中指定第一，第二和第三区域。 第一和第二区域分别是将形成半导体器件的源极和漏极的区域。 第三区域分隔第一和第二区域。 该方法还包括至少部分地在第三区域上形成开槽的注入掩模层。 该方法还包括将掺杂剂注入到第一，第二和第三区域中。 开槽植入物掩模层在植入期间保护其下方的第三区域的部分。 该方法还包括以使得掺杂剂在第三区域中扩散的方式退火衬底。

    HIGH VOLTAGE RESISTOR WITH BIASED-WELL
    15.
    发明申请
    HIGH VOLTAGE RESISTOR WITH BIASED-WELL 有权
    高压电阻器

    公开(公告)号：US20120280361A1

    公开(公告)日：2012-11-08

    申请号：US13100714

    申请日：2011-05-04

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L29/8605 ,  H01L21/02

    CPC分类号： H01L28/20 ,  H01L27/0207 ,  H01L27/0802

    摘要： Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

    摘要翻译： 提供高压半导体器件。 半导体器件包括位于衬底中的相对掺杂的掺杂阱。 半导体器件包括位于掺杂阱上的电介质结构。 邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。 半导体器件包括位于电介质结构上的细长多晶硅结构。 细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离 细长多晶硅结构。 预定距离在从大约0 * L到大约0.1 * L的范围内。

    STACKED AND TUNABLE POWER FUSE
    16.
    发明申请
    STACKED AND TUNABLE POWER FUSE 有权
    堆叠和可控电源保险丝

    公开(公告)号：US20120132995A1

    公开(公告)日：2012-05-31

    申请号：US12956025

    申请日：2010-11-30

    申请人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    发明人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L27/0288 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

    摘要翻译： 本公开提供了一种半导体器件，其包括晶体管，其包括衬底，源极，漏极和栅极以及堆叠在晶体管上的熔丝。 保险丝包括耦合到晶体管的漏极的阳极触点，阴极触点和分别经由第一肖特基二极管和第二肖特基二极管耦合到阴极触点和阳极触点的电阻器。 还提供了一种制造这种半导体器件的方法。

    SOURCE TIP OPTIMIZATION FOR HIGH VOLTAGE TRANSISTOR DEVICES
    17.
    发明申请
    SOURCE TIP OPTIMIZATION FOR HIGH VOLTAGE TRANSISTOR DEVICES 有权
    高压晶体管器件的源极优化

    公开(公告)号：US20120119265A1

    公开(公告)日：2012-05-17

    申请号：US12944959

    申请日：2010-11-12

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835

    摘要： The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

    摘要翻译： 本公开提供了一种用于制造高压半导体器件的方法。 该方法包括在衬底中指定第一，第二和第三区域。 第一和第二区域分别是将形成半导体器件的源极和漏极的区域。 第三区域分隔第一和第二区域。 该方法还包括至少部分地在第三区域上形成开槽的注入掩模层。 该方法还包括将掺杂剂注入到第一，第二和第三区域中。 开槽植入物掩模层在植入期间保护其下方的第三区域的部分。 该方法还包括以使得掺杂剂在第三区域中扩散的方式退火衬底。

    High Voltage Resistor With Pin Diode Isolation
    19.
    发明申请
    High Voltage Resistor With Pin Diode Isolation 有权
    高压电阻与引脚二极管隔离

    公开(公告)号：US20120319240A1

    公开(公告)日：2012-12-20

    申请号：US13160030

    申请日：2011-06-14

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L29/8605 ,  H01L21/20

    CPC分类号： H01L29/0649 ,  H01L21/26513 ,  H01L21/74 ,  H01L21/761 ,  H01L21/76202 ,  H01L23/528 ,  H01L27/0676 ,  H01L27/0802 ,  H01L28/20 ,  H01L29/0692 ,  H01L29/456 ,  H01L29/6609 ,  H01L29/8605 ,  H01L29/868

    摘要： Provided is a high voltage semiconductor device that includes a PIN diode structure formed in a substrate. The PIN diode includes an intrinsic region located between a first doped well and a second doped well. The first and second doped wells have opposite doping polarities and greater doping concentration levels than the intrinsic region. The semiconductor device includes an insulating structure formed over a portion of the first doped well. The semiconductor device includes an elongate resistor device formed over the insulating structure. The resistor device has first and second portions disposed at opposite ends of the resistor device, respectively. The semiconductor device includes an interconnect structure formed over the resistor device. The interconnect structure includes: a first contact that is electrically coupled to the first doped well and a second contact that is electrically coupled to a third portion of the resistor located between the first and second portions.

    摘要翻译： 提供一种高压半导体器件，其包括形成在衬底中的PIN二极管结构。 PIN二极管包括位于第一掺杂阱和第二掺杂阱之间的本征区。 第一和第二掺杂阱具有与内部区域相反的掺杂极性和更大的掺杂浓度水平。 半导体器件包括形成在第一掺杂阱的一部分上的绝缘结构。 半导体器件包括形成在绝缘结构上的细长电阻器件。 电阻器件分别设置在电阻器件的相对端处的第一和第二部分。 半导体器件包括形成在电阻器件上的互连结构。 互连结构包括：电耦合到第一掺杂阱的第一接触和电耦合到位于第一和第二部分之间的电阻器的第三部分的第二接触。