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29 条记录 (耗时 0.03 秒)

    Stacked and tunable power fuse
    2.
    发明授权
    Stacked and tunable power fuse 有权
    堆叠和可调电源保险丝

    公开(公告)号：US08598679B2

    公开(公告)日：2013-12-03

    申请号：US12956025

    申请日：2010-11-30

    申请人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    发明人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    IPC分类号： H01L23/52

    CPC分类号： H01L27/0288 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

    摘要翻译： 本公开提供了一种半导体器件，其包括晶体管，其包括衬底，源极，漏极和栅极以及堆叠在晶体管上的熔丝。 保险丝包括耦合到晶体管的漏极的阳极触点，阴极触点和分别经由第一肖特基二极管和第二肖特基二极管耦合到阴极触点和阳极触点的电阻器。 还提供了一种制造这种半导体器件的方法。

    High voltage resistor with biased-well
    4.
    发明授权
    High voltage resistor with biased-well 有权
    具有偏压井的高压电阻

    公开(公告)号：US08786050B2

    公开(公告)日：2014-07-22

    申请号：US13100714

    申请日：2011-05-04

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L21/02

    CPC分类号： H01L28/20 ,  H01L27/0207 ,  H01L27/0802

    摘要： Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

    摘要翻译： 提供高压半导体器件。 半导体器件包括位于衬底中的相对掺杂的掺杂阱。 半导体器件包括位于掺杂阱上的电介质结构。 邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。 半导体器件包括位于电介质结构上的细长多晶硅结构。 细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离 细长多晶硅结构。 预定距离在从大约0 * L到大约0.1 * L的范围内。

    Source tip optimization for high voltage transistor devices
    5.
    发明授权
    Source tip optimization for high voltage transistor devices 有权
    高压晶体管器件的源尖优化

    公开(公告)号：US08629026B2

    公开(公告)日：2014-01-14

    申请号：US12944959

    申请日：2010-11-12

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L21/22 ,  H01L21/331 ,  H01L21/336 ,  H01L21/38 ,  H01L21/425

    CPC分类号： H01L29/7816 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835

    摘要： The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

    摘要翻译： 本公开提供了一种用于制造高压半导体器件的方法。 该方法包括在衬底中指定第一，第二和第三区域。 第一和第二区域分别是将形成半导体器件的源极和漏极的区域。 第三区域分隔第一和第二区域。 该方法还包括至少部分地在第三区域上形成开槽的注入掩模层。 该方法还包括将掺杂剂注入到第一，第二和第三区域中。 开槽植入物掩模层在植入期间保护其下方的第三区域的部分。 该方法还包括以使得掺杂剂在第三区域中扩散的方式退火衬底。

    HIGH VOLTAGE RESISTOR WITH BIASED-WELL
    6.
    发明申请
    HIGH VOLTAGE RESISTOR WITH BIASED-WELL 有权
    高压电阻器

    公开(公告)号：US20120280361A1

    公开(公告)日：2012-11-08

    申请号：US13100714

    申请日：2011-05-04

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L29/8605 ,  H01L21/02

    CPC分类号： H01L28/20 ,  H01L27/0207 ,  H01L27/0802

    摘要： Provided is a high voltage semiconductor device. The semiconductor device includes a doped well located in a substrate that is oppositely doped. The semiconductor device includes a dielectric structure located on the doped well. A portion of the doped well adjacent the dielectric structure has a higher doping concentration than a remaining portion of the doped well. The semiconductor device includes an elongate polysilicon structure located on the dielectric structure. The elongate polysilicon structure has a length L. The portion of the doped well adjacent the dielectric structure is electrically coupled to a segment of the elongate polysilicon structure that is located away from a midpoint of the elongate polysilicon structure by a predetermined distance that is measured along the elongate polysilicon structure. The predetermined distance is in a range from about 0*L to about 0.1*L.

    摘要翻译： 提供高压半导体器件。 半导体器件包括位于衬底中的相对掺杂的掺杂阱。 半导体器件包括位于掺杂阱上的电介质结构。 邻近电介质结构的掺杂阱的一部分具有比掺杂阱的剩余部分更高的掺杂浓度。 半导体器件包括位于电介质结构上的细长多晶硅结构。 细长多晶硅结构具有长度L.与电介质结构相邻的掺杂阱的部分电耦合到细长多晶硅结构的段，其远离细长多晶硅结构的中点远离所测量的预定距离 细长多晶硅结构。 预定距离在从大约0 * L到大约0.1 * L的范围内。

    HV Interconnection Solution Using Floating Conductors
    7.
    发明申请
    HV Interconnection Solution Using Floating Conductors 有权
    使用浮动导体的HV互连解决方案

    公开(公告)号：US20120181629A1

    公开(公告)日：2012-07-19

    申请号：US13007220

    申请日：2011-01-14

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun-Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78

    CPC分类号： H01L29/7835 ,  H01L27/088 ,  H01L29/0692 ,  H01L29/0696 ,  H01L29/404 ,  H01L29/42368 ,  H01L29/4238 ,  H01L29/7816 ,  H01L29/861

    摘要： A device includes a first and a second heavily doped region in a semiconductor substrate. An insulation region has at least a portion in the semiconductor substrate, wherein the insulation region is adjacent to the first and the second heavily doped regions. A gate dielectric is formed over the semiconductor substrate and having a portion over a portion of the insulation region. A gate is formed over the gate dielectric. A floating conductor is over and vertically overlapping the insulation region. A metal line includes a portion over and vertically overlapping the floating conductor, wherein the metal line is coupled to, and carries a voltage of, the second heavily doped region.

    摘要翻译： 一种器件包括半导体衬底中的第一和第二重掺杂区域。 绝缘区域在半导体衬底中具有至少一部分，其中绝缘区域与第一和第二重掺杂区域相邻。 栅极电介质形成在半导体衬底之上并且具有在绝缘区域的一部分上的部分。 栅极形成在栅极电介质上。 浮动导体在绝缘区域上方和上方重叠。 金属线包括在浮动导体上方并垂直重叠的部分，其中金属线与第二重掺杂区耦合并承载第二重掺杂区的电压。

    HIGH SIDE GATE DRIVER DEVICE
    8.
    发明申请
    HIGH SIDE GATE DRIVER DEVICE 有权
    高侧门驱动装置

    公开(公告)号：US20120139041A1

    公开(公告)日：2012-06-07

    申请号：US12959538

    申请日：2010-12-03

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Ker Hsiao Huo ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L21/76202 ,  H01L27/0629 ,  H01L29/0696 ,  H01L29/1095 ,  H01L29/42368 ,  H01L29/861

    摘要： The present disclosure provides a semiconductor device. The semiconductor device includes: a drift region having a first doping polarity formed in a substrate; a doped extension region formed in the drift region and having a second doping polarity opposite the first doping polarity, the doped extension region including a laterally-extending component; a dielectric structure formed over the drift region, the dielectric structure being separated from the doped extension region by a portion of the drift region; a gate structure formed over a portion of the dielectric structure and a portion of the doped extension region; and a doped isolation region having the second doping polarity, the doped isolation region at least partially surrounding the drift region and the doped extension region.

    摘要翻译： 本发明提供一种半导体器件。 半导体器件包括：漂移区，其具有形成在衬底中的第一掺杂极性; 掺杂的延伸区域形成在所述漂移区域中并具有与所述第一掺杂极性相反的第二掺杂极性，所述掺杂延伸区域包括横向延伸的部件; 在所述漂移区上形成的电介质结构，所述电介质结构通过所述漂移区的一部分与所述掺杂延伸区分离; 形成在电介质结构的一部分上的栅结构和掺杂延伸区的一部分; 以及具有第二掺杂极性的掺杂隔离区，所述掺杂隔离区至少部分地围绕所述漂移区和所述掺杂延伸区。

    STACKED AND TUNABLE POWER FUSE
    9.
    发明申请
    STACKED AND TUNABLE POWER FUSE 有权
    堆叠和可控电源保险丝

    公开(公告)号：US20120132995A1

    公开(公告)日：2012-05-31

    申请号：US12956025

    申请日：2010-11-30

    申请人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    发明人： Chih-Chang Cheng ,  Ruey-Hsin Liu ,  Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai

    IPC分类号： H01L27/06 ,  H01L21/02

    CPC分类号： H01L27/0288 ,  H01L23/5256 ,  H01L27/0255 ,  H01L27/0629 ,  H01L2924/0002 ,  H01L2924/00

    摘要： The present disclosure provides a semiconductor device that includes a transistor including a substrate, a source, a drain, and a gate, and a fuse stacked over the transistor. The fuse includes an anode contact coupled to the drain of the transistor, a cathode contact, and a resistor coupled to the cathode contact and the anode contact via a first Schottky diode and a second Schottky diode, respectively. A method of fabricating such semiconductor devices is also provided.

    摘要翻译： 本公开提供了一种半导体器件，其包括晶体管，其包括衬底，源极，漏极和栅极以及堆叠在晶体管上的熔丝。 保险丝包括耦合到晶体管的漏极的阳极触点，阴极触点和分别经由第一肖特基二极管和第二肖特基二极管耦合到阴极触点和阳极触点的电阻器。 还提供了一种制造这种半导体器件的方法。

    SOURCE TIP OPTIMIZATION FOR HIGH VOLTAGE TRANSISTOR DEVICES
    10.
    发明申请
    SOURCE TIP OPTIMIZATION FOR HIGH VOLTAGE TRANSISTOR DEVICES 有权
    高压晶体管器件的源极优化

    公开(公告)号：US20120119265A1

    公开(公告)日：2012-05-17

    申请号：US12944959

    申请日：2010-11-12

    申请人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    发明人： Ru-Yi Su ,  Fu-Chih Yang ,  Chun Lin Tsai ,  Chih-Chang Cheng ,  Ruey-Hsin Liu

    IPC分类号： H01L29/78 ,  H01L21/22 ,  H01L21/336

    CPC分类号： H01L29/7816 ,  H01L21/2253 ,  H01L21/26513 ,  H01L29/0634 ,  H01L29/0847 ,  H01L29/0878 ,  H01L29/105 ,  H01L29/42368 ,  H01L29/66659 ,  H01L29/66681 ,  H01L29/66795 ,  H01L29/7835

    摘要： The present disclosure provides a method for fabricating a high-voltage semiconductor device. The method includes designating first, second, and third regions in a substrate. The first and second regions are regions where a source and a drain of the semiconductor device will be formed, respectively. The third region separates the first and second regions. The method further includes forming a slotted implant mask layer at least partially over the third region. The method also includes implanting dopants into the first, second, and third regions. The slotted implant mask layer protects portions of the third region therebelow during the implanting. The method further includes annealing the substrate in a manner to cause diffusion of the dopants in the third region.

    摘要翻译： 本公开提供了一种用于制造高压半导体器件的方法。 该方法包括在衬底中指定第一，第二和第三区域。 第一和第二区域分别是将形成半导体器件的源极和漏极的区域。 第三区域分隔第一和第二区域。 该方法还包括至少部分地在第三区域上形成开槽的注入掩模层。 该方法还包括将掺杂剂注入到第一，第二和第三区域中。 开槽植入物掩模层在植入期间保护其下方的第三区域的部分。 该方法还包括以使得掺杂剂在第三区域中扩散的方式退火衬底。