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公开(公告)号：US08151149B2
公开(公告)日：2012-04-03
申请号：US12649743
申请日：2009-12-30
Applicant: Jeong-Hun Lee , Yong-Mi Kim , Jeong-Tea Hwang
Inventor： Jeong-Hun Lee , Yong-Mi Kim , Jeong-Tea Hwang
IPC: G11C29/00
CPC classification number: G11C29/46
Abstract: A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.
Abstract translation: 根据实施例的半导体存储装置包括测试模式控制器，第一数据对准单元，解码器，测试执行单元和第二数据对准单元。 测试模式控制器被配置为响应于测试模式设置信号和读取命令而产生测试使能信号。 第一数据对准单元被配置为并行地对准串联输入的第一输入数据，产生第一对准数据，并将其发送到第一数据驱动器。 解码器被配置为响应于测试使能信号解码第一对准数据并产生解码信号。 测试执行单元被配置为响应于解码信号执行预设测试模式。 第二数据对准单元被配置为响应于测试使能信号并行输入串联的第二输入数据，产生第二对准数据并将其发送到第二数据驱动器。
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公开(公告)号：US08037372B2
公开(公告)日：2011-10-11
申请号：US12346663
申请日：2008-12-30
Applicant: Jeong-Hun Lee
Inventor： Jeong-Hun Lee
CPC classification number: G11C29/02 , G11C29/023 , G11C29/028
Abstract: An apparatus for testing setup/hold time includes a plurality of data input units, each configured to calibrate setup/hold time of input data in response to selection signals and setup/hold calibration signals, and an off-chip driver calibration unit configured to generate the selection signals and the setup/hold calibration signals by using the input data input of one of the plurality of data input units.
Abstract translation: 用于测试建立/保持时间的装置包括多个数据输入单元，每个数据输入单元被配置为响应于选择信号和建立/保持校准信号来校准输入数据的建立/保持时间，以及片外驱动器校准单元， 所述选择信号和所述建立/保持校准信号通过使用所述多个数据输入单元之一的输入数据输入。
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公开(公告)号：US20110004794A1
公开(公告)日：2011-01-06
申请号：US12616529
申请日：2009-11-11
Applicant: Jeong-Hun Lee , Jeong-Tae Hwang
Inventor： Jeong-Hun Lee , Jeong-Tae Hwang
IPC: G11C29/10 , G06F11/263
CPC classification number: G11C29/46
Abstract: A semiconductor memory device is capable of performing a test operation in its various operation modes. Particularly, the semiconductor memory device can enter a test mode in other modes, as well as, an all bank pre-charge mode. The semiconductor memory device includes a test mode control block configured to generate a test signal enabled for a predetermined interval in an active mode, and a mode register set control block configured to enable a mode register set signal for a test operation in the predetermined interval in response to the test signal.
Abstract translation: 半导体存储器件能够在其各种操作模式下执行测试操作。 特别地，半导体存储器件可以进入其他模式的测试模式以及全部银行预充电模式。 半导体存储器件包括：测试模式控制块，被配置为在激活模式下产生预定间隔使能的测试信号;以及模式寄存器组控制模块，被配置为使得模式寄存器设置信号能够在预定间隔内进行测试操作 响应测试信号。
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14.发明申请公开(公告)号：US20100290304A1
公开(公告)日：2010-11-18
申请号：US12494815
申请日：2009-06-30
Applicant: Jeong-Hun Lee , Yong-Mi Kim , Jeong-Tae Hwang
Inventor： Jeong-Hun Lee , Yong-Mi Kim , Jeong-Tae Hwang
IPC: G11C5/14
Abstract: A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.
Abstract translation: 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。
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