公开(公告)号：US08151149B2

公开(公告)日：2012-04-03

申请号：US12649743

申请日：2009-12-30

申请人： Jeong-Hun Lee ,  Yong-Mi Kim ,  Jeong-Tea Hwang

发明人： Jeong-Hun Lee ,  Yong-Mi Kim ,  Jeong-Tea Hwang

IPC分类号： G11C29/00

CPC分类号： G11C29/46

摘要： A semiconductor memory apparatus according to the embodiment includes a test mode controller, a first data alignment unit, a decoder, a test executing unit and a second data alignment unit. The test mode controller is configured to generate test enable signals in response to a test mode setting signal and a read command. The first data alignment unit is configured to parallely align first input data that are input in series, generate first alignment data, and transmit it to the first data driver. The decoder is configured to decode the first alignment data in response to the test enable signal and generate the decoding signal. The test executing unit is configured to execute the preset test mode in response to the decoding signal. The second data alignment unit is configured to parallely align second input data, which are input in series, in response to the test enable signal, generate second alignment data, and transmit it to a second data driver.

摘要翻译： 根据实施例的半导体存储装置包括测试模式控制器，第一数据对准单元，解码器，测试执行单元和第二数据对准单元。 测试模式控制器被配置为响应于测试模式设置信号和读取命令而产生测试使能信号。 第一数据对准单元被配置为并行地对准串联输入的第一输入数据，产生第一对准数据，并将其发送到第一数据驱动器。 解码器被配置为响应于测试使能信号解码第一对准数据并产生解码信号。 测试执行单元被配置为响应于解码信号执行预设测试模式。 第二数据对准单元被配置为响应于测试使能信号并行输入串联的第二输入数据，产生第二对准数据并将其发送到第二数据驱动器。

公开(公告)号：US07983106B2

公开(公告)日：2011-07-19

申请号：US12494815

申请日：2009-06-30

申请人： Yong-Mi Kim ,  Jeong-Tea Hwang ,  Jeong-Hun Lee

发明人： Yong-Mi Kim ,  Jeong-Tea Hwang ,  Jeong-Hun Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

摘要： A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

摘要翻译： 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。

公开(公告)号：US08320212B2

公开(公告)日：2012-11-27

申请号：US13155901

申请日：2011-06-08

申请人： Yong-Mi Kim ,  Jeong-Tae Hwang ,  Jeong-Hun Lee

发明人： Yong-Mi Kim ,  Jeong-Tae Hwang ,  Jeong-Hun Lee

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

摘要： A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

摘要翻译： 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。

公开(公告)号：US20100290304A1

公开(公告)日：2010-11-18

申请号：US12494815

申请日：2009-06-30

申请人： Jeong-Hun Lee ,  Yong-Mi Kim ,  Jeong-Tae Hwang

发明人： Jeong-Hun Lee ,  Yong-Mi Kim ,  Jeong-Tae Hwang

IPC分类号： G11C5/14

CPC分类号： G11C5/147 ,  G11C7/02 ,  G11C7/22 ,  G11C7/222

摘要： A voltage stabilization circuit of a semiconductor memory apparatus includes an operation speed detecting unit configured to detect an operation speed of the semiconductor memory apparatus to generate a detection signal, and a voltage line controlling unit configured to interconnect a first voltage line and a second voltage line in response to the detection signal.

摘要翻译： 半导体存储装置的电压稳定电路包括操作速度检测单元，其被配置为检测半导体存储装置的操作速度以产生检测信号;以及电压线控制单元，被配置为将第一电压线和第二电压线 响应于检测信号。

公开(公告)号：US07372294B2

公开(公告)日：2008-05-13

申请号：US11478084

申请日：2006-06-30

申请人： Yong-Mi Kim

发明人： Yong-Mi Kim

IPC分类号： H03K19/003

CPC分类号： H04L25/0298 ,  G11C7/1048 ,  G11C7/1066 ,  G11C29/02 ,  G11C29/025 ,  G11C29/50008

摘要： An on-die termination apparatus guarantees a desirable spec margin by separately controlling pull-up transistors and pull-down transistors provided in a main on-die termination block. The on-die termination circuit includes an extended mode register set decoding unit for decoding an inputted address to output a plurality of decoding signals to set a termination impedance; an ODT control unit for selectively activating a plurality of pull-up control signals and a multiplicity of pull-down control signals by logically combining the plurality of decoding signals, pull-up test signals and pull-down test signals; and an ODT unit including a plurality of main termination units to test the termination impedance by separately activating the plurality of main termination units based on the plurality of pull-up control signals and the multiplicity of pull-down control signals.

摘要翻译： 片上端接装置通过单独控制设置在主片上端接块中的上拉晶体管和下拉晶体管来保证期望的规格裕度。 片上终端电路包括扩展模式寄存器组解码单元，用于解码输入的地址以输出多个解码信号以设置终端阻抗; ODT控制单元，用于通过逻辑组合多个解码信号，上拉测试信号和下拉测试信号来选择性地激活多个上拉控制信号和多个下拉控制信号; 以及ODT单元，其包括多个主终端单元，用于基于所述多个上拉控制信号和多个下拉控制信号单独激活所述多个主终端单元来测试终端阻抗。

公开(公告)号：US20060139060A1

公开(公告)日：2006-06-29

申请号：US11124317

申请日：2005-05-06

申请人： Yong-Mi Kim

发明人： Yong-Mi Kim

IPC分类号： H03K19/094

CPC分类号： H03K5/133 ,  G11C7/1051 ,  G11C7/1057 ,  G11C7/1078 ,  G11C7/1084 ,  H03K19/018585

摘要： A semiconductor memory device is capable of adjusting effective data period of data. The semiconductor memory device includes a buffering unit for buffering input data, a window adjusting unit, and a transmitting unit. The window adjusting unit is for adjusting a window of the buffered data outputted from the buffering unit in response to plural metal option. The window adjusting unit includes a first driving unit for driving an output node in response to the output signal from the buffering unit and a second driving unit for additionally driving the output node in response to the output signal from the buffering unit. Meanwhile, the transmitting unit delivers output of the window adjusting unit into a core block.

摘要翻译： 半导体存储器件能够调节数据的有效数据周期。 半导体存储器件包括用于缓冲输入数据的缓冲单元，窗口调整单元和发送单元。 窗口调整单元用于响应于多个金属选项来调整从缓冲单元输出的缓冲数据的窗口。 窗口调整单元包括用于响应于来自缓冲单元的输出信号驱动输出节点的第一驱动单元和用于响应于来自缓冲单元的输出信号另外驱动输出节点的第二驱动单元。 同时，发送单元将窗口调整单元的输出传递到核心块中。

公开(公告)号：US20060091901A1

公开(公告)日：2006-05-04

申请号：US11070367

申请日：2005-03-01

申请人： Yong-Mi Kim

发明人： Yong-Mi Kim

IPC分类号： H03K19/003

CPC分类号： G11C7/1051 ,  G11C7/1057

摘要： An on-die termination circuit with a stable effective termination resistance value and stabilized impedance mismatching. The on-die termination circuit includes: a decoding unit for decoding set values of an extended mode register set; an ODT output driver block including a plurality of output driver units connected in parallel with an output node for outputting an output signal and assigned with different resistance values; and a control signal generation block for generating a plurality of pull up and pull down control signals for turning on/off the plurality of output driver units in response to output signals of the decoding unit.

摘要翻译： 具有稳定的有效终端电阻值和稳定的阻抗失配的片上终端电路。 片上终端电路包括：解码单元，用于解码扩展模式寄存器组的设定值; ODT输出驱动器块，包括与输出节点并联连接的多个输出驱动器单元，用于输出输出信号并分配有不同的电阻值; 以及控制信号生成块，用于响应于解码单元的输出信号产生用于接通/关闭多个输出驱动器单元的多个上拉和下拉控制信号。

公开(公告)号：US20050024911A1

公开(公告)日：2005-02-03

申请号：US10744156

申请日：2003-12-22

申请人： Yong-Mi Kim

发明人： Yong-Mi Kim

IPC分类号： G11C5/14 ,  G11C11/4074 ,  G11C17/00

CPC分类号： G11C5/14

摘要： There is provided a semiconductor memory device which is capable of reducing a current consumption in an active mode. The semiconductor memory device includes an internal voltage supply block and an internal voltage control block. The internal voltage supplying block is enabled in response to an internal voltage driving enable signal and generates an internal voltage used in an internal operation of the semiconductor memory device. The internal voltage control block activates the internal voltage driving enable signal during a predetermined period after the semiconductor memory device enters an active operation period and during a period corresponding to read/write operations.

摘要翻译： 提供了能够在活动模式中减少电流消耗的半导体存储器件。 半导体存储器件包括内部电压供应块和内部电压控制块。 内部电压供应块响应于内部电压驱动使能信号而使能，并产生在半导体存储器件的内部操作中使用的内部电压。 内部电压控制块在半导体存储器件进入有效操作时段之后的预定时间段期间和对应于读取/写入操作的时段期间激活内部电压驱动使能信号。

公开(公告)号：US08633748B2

公开(公告)日：2014-01-21

申请号：US13302167

申请日：2011-11-22

申请人： Hye-Young Lee ,  Yong-Mi Kim

发明人： Hye-Young Lee ,  Yong-Mi Kim

IPC分类号： H03L7/06

CPC分类号： H03L7/0814 ,  H03K2005/00241 ,  H03L7/0816 ,  H03L7/093

摘要： A filtering circuit includes jitter determination reference control unit configured to determine a jitter determination reference in correspondence to an operation mode and output a control signal in response to the jitter determination reference, and a filtering unit configured to set the jitter determination reference in response to the control signal and determine whether an input signal is maintained during a sample period in response to the set jitter determination reference.

摘要翻译： 滤波电路包括：抖动判定基准控制部，被配置为根据操作模式确定抖动判定基准，响应抖动判定基准输出控制信号;滤波部，被配置为响应于抖动判定基准 控制信号，并且响应于所设置的抖动判定参考，确定在采样周期期间是否维持输入信号。

公开(公告)号：US08476923B2

公开(公告)日：2013-07-02

申请号：US13334022

申请日：2011-12-21

申请人： Dong-Wook Jang ,  Yong-Mi Kim

发明人： Dong-Wook Jang ,  Yong-Mi Kim

IPC分类号： H03K17/16

CPC分类号： H03K19/0005

摘要： A circuit, including a first impedance unit having an impedance value based on a first impedance code and configured to drive a first node coupled with a resistor with a first voltage, a first code generation unit configured to generate the first impedance code so that an impedance value of the first impedance unit and an impedance value of the resistor are at a ratio of X:Y, dummy impedance units that receive the first impedance code and drive a second node with the first voltage, a second impedance unit having an impedance value based on a second impedance code and configured to drive the second node with a second voltage, and a second code generation unit configured to generate the second impedance code so that an overall impedance value of the dummy impedance units and an impedance value of the second impedance unit are at a ratio of X:Y.

摘要翻译： 一种电路，包括具有基于第一阻抗码的阻抗值并被配置为驱动与第一电压耦合的电阻器的第一节点的第一阻抗单元，第一代码产生单元，被配置为产生第一阻抗代码，使得阻抗 第一阻抗单元的值和电阻器的阻抗值为X:Y，接收第一阻抗代码的虚拟阻抗单元和驱动具有第一电压的第二节点的比例，具有基于阻抗值的第二阻抗单元 在第二阻抗代码上并被配置为以第二电压驱动第二节点，以及第二代码生成单元，被配置为生成第二阻抗代码，使得虚拟阻抗单元的总阻抗值和第二阻抗单元的阻抗值 是X：Y的比例。