公开(公告)号：US07577025B2

公开(公告)日：2009-08-18

申请号：US11841058

申请日：2007-08-20

申请人： Jin-Young Kim ,  Ki-Whan Song ,  Duk-Ha Park

发明人： Jin-Young Kim ,  Ki-Whan Song ,  Duk-Ha Park

IPC分类号： G11C11/34

CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C11/4091 ,  G11C2211/4016

摘要： A semiconductor device comprising floating body memory cells performs read and write operations by selectively connecting bit lines and inverted bit lines to sense bit lines and inverted sense bit lines.

摘要翻译： 包括浮体存储单元的半导体器件通过选择性地连接位线和反相位线来读取和写入操作来读取位线和反相检测位线。

公开(公告)号：US20090103343A1

公开(公告)日：2009-04-23

申请号：US11797867

申请日：2007-05-08

申请人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

发明人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

IPC分类号： G11C5/02 ,  G11C7/00 ,  G11C8/08 ,  G11C5/06

CPC分类号： H01L27/10876 ,  G11C7/1042 ,  G11C7/12 ,  G11C11/404 ,  G11C11/4094 ,  H01L29/78 ,  H01L29/7827

摘要： A semiconductor memory device including a transistor having a vertical channel structure is provided. The device comprises a first sub memory cell array comprising a first memory cell connected to a first bit lines and comprising a transistor having a vertical channel structure, a second sub memory cell array comprising a second memory cell connected to a first inverted bit lines and comprising a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.

摘要翻译： 提供一种包括具有垂直沟道结构的晶体管的半导体存储器件。 该器件包括第一子存储器单元阵列，该第一子存储单元阵列包括连接到第一位线的第一存储器单元，并且包括具有垂直沟道结构的晶体管，第二子存储单元阵列，包括连接到第一反相位线的第二存储单元， 具有垂直沟道结构的晶体管和多个预充电块。 此外，第一和第二预充电块设置在第一位线的第一和第二侧并对第一位线进行预充电，并且第三和第四预充电块设置在第一反相位线的第一和第二侧，并且对第一 反转位线。

公开(公告)号：US20090097332A1

公开(公告)日：2009-04-16

申请号：US12285520

申请日：2008-10-08

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： G11C7/00 ,  G11C8/08

CPC分类号： G11C5/147 ,  G11C11/4076 ,  G11C11/4091 ,  G11C11/4094 ,  G11C2211/4016

摘要： A semiconductor memory device includes a memory cell array including a plurality of memory cells having a transistor with a floating body, a source line driver configured to control the source lines to select the memory cells in response to an address signal, a source line voltage generation unit configured to generate a source line target voltage, receive an source line output voltage from the source line driver, compare the level of the source line output voltage with the level of the source line target voltage, generate a source line voltage of which the level is adaptively varied according to a temperature, and a sense amplifier configured to sense a difference in current flowing through the bit lines in response to data read from a selected memory cell, amplify the difference to a level having high output driving capability and output the amplified current.

摘要翻译： 半导体存储器件包括存储单元阵列，该存储单元阵列包括具有浮置体的晶体管的多个存储器单元，源极线驱动器，被配置为响应于地址信号控制源极线选择存储单元，源极线电压产生 被配置为产生源极线路目标电压的单元，从源极线驱动器接收源极线路输出电压，将源极线路输出电压的电平与源极线路目标电压的电平进行比较，生成源极线电压， 根据温度自适应地变化;以及读出放大器，被配置为响应于从选择的存储单元读取的数据来感测流过位线的电流差，将该差放大到具有高输出驱动能力的电平，并输出放大的 当前。

公开(公告)号：US20070159903A1

公开(公告)日：2007-07-12

申请号：US11546421

申请日：2006-10-12

申请人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

发明人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

IPC分类号： G11C7/02

CPC分类号： G11C11/405 ,  G11C7/065 ,  G11C11/4091 ,  G11C2211/4016

摘要： In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary first and second bit lines, and a voltage sense amplifier coupled between the complementary first and second bit lines which amplifies a voltage differential between the complementary first and second bit lines.

摘要翻译： 一方面，提供了包括互补的第一和第二位线的半导体存储器件，包括分别耦合到互补的第一和第二位线的互补的第一和第二浮体晶体管无电容器存储器单元的单元存储单元，以及电压读出放大器 耦合在互补的第一和第二位线之间，互补的第一和第二位线放大互补的第一和第二位线之间的电压差。

公开(公告)号：US08274810B2

公开(公告)日：2012-09-25

申请号：US12955090

申请日：2010-11-29

申请人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

发明人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

IPC分类号： G11C5/02

CPC分类号： H01L27/10876 ,  G11C7/1042 ,  G11C7/12 ,  G11C11/404 ,  G11C11/4094 ,  H01L29/78 ,  H01L29/7827

摘要： A semiconductor memory device including a transistor having a vertical channel structure is provided. The device includes a first sub memory cell array including a first memory cell connected to a first bit lines and including a transistor having a vertical channel structure, a second sub memory cell array including a second memory cell connected to a first inverted bit lines and including a transistor having a vertical channel structure, and a plurality of precharge blocks. In addition, first and second precharge blocks are disposed at first and second sides of the first bit line and precharge the first bit line, and third and fourth precharge blocks are disposed at first and second sides of the first inverted bit line and precharge the first inverted bit line.

摘要翻译： 提供一种包括具有垂直沟道结构的晶体管的半导体存储器件。 该器件包括第一子存储单元阵列，该第一子存储单元阵列包括连接到第一位线并包括具有垂直沟道结构的晶体管的第一存储单元，第二子存储单元阵列，包括连接到第一反相位线的第二存储单元， 具有垂直沟道结构的晶体管和多个预充电块。 此外，第一和第二预充电块设置在第一位线的第一和第二侧并对第一位线进行预充电，并且第三和第四预充电块设置在第一反相位线的第一和第二侧，并且对第一 反转位线。

公开(公告)号：US20100118631A1

公开(公告)日：2010-05-13

申请号：US12591196

申请日：2009-11-12

申请人： Jin-Young Kim ,  Chul-Woo Park ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Chul-Woo Park ,  Ki-Whan Song

IPC分类号： G11C7/00 ,  G11C7/06

CPC分类号： G11C11/4099 ,  G11C11/4091

摘要： A semiconductor memory device having the mismatch cell makes a capacitance difference between a bit line pair relatively large during a read operation using at least one dummy memory cell as a mismatch cell selected together with a corresponding memory cell. Therefore, data of a semiconductor memory device may be detected more easily.

摘要翻译： 具有不匹配单元的半导体存储器件在使用至少一个虚拟存储器单元作为与对应的存储器单元一起选择的不匹配单元的读取操作期间，位线对之间的电容差相对较大。 因此，可以更容易地检测半导体存储器件的数据。

公开(公告)号：US07701793B2

公开(公告)日：2010-04-20

申请号：US11882931

申请日：2007-08-07

申请人： Jin-Young Kim ,  Ki-Whan Song ,  Duk-Ha Park

发明人： Jin-Young Kim ,  Ki-Whan Song ,  Duk-Ha Park

IPC分类号： G11C7/00

CPC分类号： G11C11/4091 ,  G11C11/4096 ,  G11C2207/002 ,  G11C2207/005 ,  G11C2211/4016

摘要： One embodiment includes a plurality of word lines, a plurality of bit lines intersecting with the plurality of word lines, a plurality of memory cells formed at intersections of and connected to the plurality of word lines and the plurality of bit lines. Each of the plurality of memory cells may be a floating body cell. A bit line selecting circuit may be configured to selectively connect each of the plurality of bit lines to an output bit line. The embodiment may further include plurality of sense amplifiers, where the plurality of sense amplifiers is greater than one and less than the plurality of bit lines in number. A sense amplifier switching structure may be configured to selectively connect each of the plurality of sense amplifiers to the output bit line.

摘要翻译： 一个实施例包括多个字线，与多个字线相交的多个位线，多个存储单元，形成在多个字线和多个位线的交叉点处并与之连接。 多个存储单元中的每一个可以是浮动体单元。 位线选择电路可以被配置为选择性地将多个位线中的每一个连接到输出位线。 该实施例还可以包括多个读出放大器，其中多个读出放大器的数量大于一个且小于多个位线。 读出放大器切换结构可以被配置为选择性地将多个读出放大器中的每一个连接到输出位线。

公开(公告)号：US20090302897A1

公开(公告)日：2009-12-10

申请号：US12457240

申请日：2009-06-04

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： H03K3/00

CPC分类号： H03K19/018521 ,  G11C8/08 ,  G11C11/4085

摘要： Example embodiments relate to a driver circuit and a semiconductor memory device including the driver circuit. The driver circuit includes a pull-up unit configured to connect an output node to a first power supply voltage in response to an input signal, an interface unit connected between the output node and a first node to decrease a voltage of the output node in response to a control signal, and a pull-down unit configured to connect the first node to a second power supply voltage. The interface unit includes a first transistor configured to connect the output node with the first node in response to the control signal and a first resistor connected between the output node and the first node. The interface unit may also include a second resistor and a second transistor connected in series between the output node and the first node.

摘要翻译： 示例实施例涉及包括驱动器电路的驱动器电路和半导体存储器件。 驱动器电路包括上拉单元，其被配置为响应于输入信号将输出节点连接到第一电源电压，连接在输出节点和第一节点之间的接口单元，以响应地降低输出节点的电压 以及被配置为将第一节点连接到第二电源电压的下拉单元。 接口单元包括第一晶体管，其被配置为响应于控制信号将输出节点与第一节点连接，以及连接在输出节点和第一节点之间的第一电阻器。 接口单元还可以包括串联连接在输出节点和第一节点之间的第二电阻器和第二晶体管。

公开(公告)号：US07619928B2

公开(公告)日：2009-11-17

申请号：US11943653

申请日：2007-11-21

申请人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

发明人： Duk-Ha Park ,  Ki-Whan Song ,  Jin-Young Kim

IPC分类号： G11C11/03

CPC分类号： G11C11/404 ,  G11C11/4076 ,  G11C2211/4016

摘要： A semiconductor memory device includes first and second memory cells having floating bodies, each of which includes a gate connected to a word line and an electrode connected to a common source line to store data. A controller applies a first voltage to the common source line, a negative second voltage to the word line, a third voltage as a first sense enable control voltage and the first voltage as a second sense enable control voltage during a first write period of a write operation. The controller also applies a fourth voltage to the common source line and the first voltage to the word line during a second write period of the write operation. The sensing portion amplifies a bit line and an inverted bit line to the third voltage or the first voltage, respectively, during the first write period in response to the first and second sense enable control voltages.

摘要翻译： 半导体存储器件包括具有浮体的第一和第二存储单元，每个浮体包括连接到字线的栅极和连接到公共源极线以存储数据的电极。 控制器在写入的第一写入周期期间将第一电压施加到公共源极线，对字线施加负的第二电压，将第三电压作为第一感测使能控制电压施加第一电压，将第一电压作为第二感测使能控制电压 操作。 在写入操作的第二写入周期期间，控制器还向公共源极线施加第四电压并将第一电压施加到字线。 响应于第一和第二感测使能控制电压，感测部分在第一写入周期期间分别将位线和反相位线放大到第三电压或第一电压。

公开(公告)号：US07977736B2

公开(公告)日：2011-07-12

申请号：US11801915

申请日：2007-02-08

申请人： Jin-Young Kim ,  Ki-Whan Song

发明人： Jin-Young Kim ,  Ki-Whan Song

IPC分类号： H01L29/66

CPC分类号： H01L21/823842 ,  H01L21/823885 ,  H01L27/092 ,  H01L27/105 ,  H01L27/1052

摘要： A semiconductor device is provided which includes an NMOS vertical channel transistor located on a substrate and including a p+ polysilicon gate electrode surrounding a vertical p-channel region, and a PMOS vertical channel transistor located on the substrate and including an n+ polysilicon gate electrode surrounding a vertical n-channel region. The NMOS and PMOS vertical channel transistors are optionally operable in a CMOS operational mode.

摘要翻译： 提供了一种半导体器件，其包括位于衬底上并包括围绕垂直p沟道区的p +多晶硅栅电极的NMOS垂直沟道晶体管和位于衬底上的PMOS垂直沟道晶体管，并且包括n + 垂直n沟道区域。 NMOS和PMOS垂直沟道晶体管可选地以CMOS操作模式工作。