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    Memory devices including floating body transistor capacitorless memory cells and related methods
    1.
    发明申请
    Memory devices including floating body transistor capacitorless memory cells and related methods 有权
    存储器件包括浮体晶体管无电容存储单元及相关方法

    公开(公告)号：US20070159903A1

    公开(公告)日：2007-07-12

    申请号：US11546421

    申请日：2006-10-12

    申请人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

    发明人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

    IPC分类号： G11C7/02

    CPC分类号： G11C11/405 ,  G11C7/065 ,  G11C11/4091 ,  G11C2211/4016

    摘要： In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary first and second bit lines, and a voltage sense amplifier coupled between the complementary first and second bit lines which amplifies a voltage differential between the complementary first and second bit lines.

    摘要翻译： 一方面，提供了包括互补的第一和第二位线的半导体存储器件，包括分别耦合到互补的第一和第二位线的互补的第一和第二浮体晶体管无电容器存储器单元的单元存储单元，以及电压读出放大器 耦合在互补的第一和第二位线之间，互补的第一和第二位线放大互补的第一和第二位线之间的电压差。

    Memory devices including floating body transistor capacitorless memory cells and related methods
    2.
    发明授权
    Memory devices including floating body transistor capacitorless memory cells and related methods 有权
    存储器件包括浮体晶体管无电容存储单元及相关方法

    公开(公告)号：US07433223B2

    公开(公告)日：2008-10-07

    申请号：US11546421

    申请日：2006-10-12

    申请人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

    发明人： Jin-Young Kim ,  Ki-Whan Song ,  Yeong-Taek Lee

    IPC分类号： G11C11/24

    CPC分类号： G11C11/405 ,  G11C7/065 ,  G11C11/4091 ,  G11C2211/4016

    摘要： In one aspect, a semiconductor memory device is provided which includes complementary first and second bit lines, a unit memory cell including complementary first and second floating body transistor capacitorless memory cells respectively coupled to the complementary first and second bit lines, and a voltage sense amplifier coupled between the complementary first and second bit lines which amplifies a voltage differential between the complementary first and second bit lines.

    摘要翻译： 一方面，提供了包括互补的第一和第二位线的半导体存储器件，包括分别耦合到互补的第一和第二位线的互补的第一和第二浮体晶体管无电容器存储器单元的单元存储单元，以及电压读出放大器 耦合在互补的第一和第二位线之间，互补的第一和第二位线放大互补的第一和第二位线之间的电压差。

    Semiconductor memory devices and methods of arranging memory cell arrays thereof
    3.
    发明授权
    Semiconductor memory devices and methods of arranging memory cell arrays thereof 失效
    半导体存储器件及其排列存储单元阵列的方法

    公开(公告)号：US08179707B2

    公开(公告)日：2012-05-15

    申请号：US12453595

    申请日：2009-05-15

    申请人： Ki-Whan Song ,  Yeong-Taek Lee

    发明人： Ki-Whan Song ,  Yeong-Taek Lee

    IPC分类号： G11C5/02

    CPC分类号： G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4097 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2211/4016 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891

    摘要： Semiconductor memory devices with a memory cell array including a first word line and a second word line arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a first bit line and a second bit line arranged in a second direction perpendicular to the first direction, a first memory cell including a gate connected to the first word line and first and second regions respectively connected to the second bit line and the source line, and arranged in a third direction between the first direction and the second direction, and a second memory cell including a gate connected to the second word line, a third region and the second region respectively connected to the first bit line and the source line, and arranged in the third direction.

    摘要翻译： 具有包括沿第一方向布置的第一字线和第二字线的存储单元阵列的半导体存储器件，在第一字线和第二字线之间沿第一方向布置的源极线，包括第一 位线和与第一方向垂直的第二方向排列的第二位线，第一存储单元，包括连接到第一字线的栅极和分别连接到第二位线和源极线的第一和第二区域，并且布置 在第一方向和第二方向之间的第三方向上，以及第二存储单元，包括连接到第二字线的栅极，分别连接到第一位线和源极线的第三区域和第二区域，并且布置在 第三个方向。

    Silicon-controlled rectifier for electrostatic discharge protection circuits and structure thereof
    4.
    发明授权
    Silicon-controlled rectifier for electrostatic discharge protection circuits and structure thereof 有权
    用于静电放电保护电路的可控硅整流器及其结构

    公开(公告)号：US07633096B2

    公开(公告)日：2009-12-15

    申请号：US11461681

    申请日：2006-08-01

    申请人： Ki-Whan Song ,  Yeong-Taek Lee

    发明人： Ki-Whan Song ,  Yeong-Taek Lee

    IPC分类号： H01L23/62

    CPC分类号： H01L27/0262

    摘要： A Silicon-Controlled Rectifier (SCR) for Electrostatic Discharge (ESD) protection includes an isolation device. The isolation device isolates a main ground voltage line, connected to a first cathode, from a peripheral ground voltage line, connected to a second cathode. As result, even when noise occurs in the peripheral ground voltage line during the operation of an integrated circuit, the main ground voltage line maintains a stable voltage level.

    摘要翻译： 用于静电放电（ESD）保护的硅控整流器（SCR）包括隔离装置。 隔离装置将连接到第一阴极的主接地电压线与连接到第二阴极的外围接地电压线隔离。 因此，即使在集成电路的动作中，外围接地电压线发生噪声时，主接地电压线保持稳定的电压电平。

    Semiconductor memory devices and methods of arranging memory cell arrays thereof
    5.
    发明申请
    Semiconductor memory devices and methods of arranging memory cell arrays thereof 失效
    半导体存储器件及其排列存储单元阵列的方法

    公开(公告)号：US20090290402A1

    公开(公告)日：2009-11-26

    申请号：US12453595

    申请日：2009-05-15

    申请人： Ki-Whan Song ,  Yeong-Taek Lee

    发明人： Ki-Whan Song ,  Yeong-Taek Lee

    IPC分类号： G11C5/02 ,  G11C5/06 ,  G11C7/06 ,  G11C8/08

    CPC分类号： G11C7/18 ,  G11C8/08 ,  G11C8/14 ,  G11C11/4097 ,  G11C13/00 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C2211/4016 ,  G11C2213/79 ,  H01L27/0207 ,  H01L27/108 ,  H01L27/10802 ,  H01L27/10891

    摘要： A semiconductor memory device and a method of arranging a memory cell array of the semiconductor device are provided. The semiconductor memory device has a memory cell array including a word line pair including a first word line and a second word line that are arranged in a first direction, a source line arranged in the first direction between the first word line and the second word line, a bit line pair including a first bit line and a second bit line arranged in a second direction perpendicular to the first direction, a first memory cell including a gate connected to the first word line and first and second regions respectively connected to the second bit line and the source line, and arranged in a third direction between the first direction and the second direction, and a second memory cell including a gate connected to the second word line, a third region and the second region respectively connected to the first bit line and the source line, and arranged in the third direction. The first word line and the second word line are simultaneously activated. Therefore, disturbance that may be generated between adjacent memory cells in the semiconductor memory cell can be prevented, integration density of the semiconductor memory device can be enhanced, and the number of word lines to be driven may be reduced to employ a sub-word line structure.

    摘要翻译： 提供半导体存储器件和布置半导体器件的存储单元阵列的方法。 半导体存储器件具有存储单元阵列，该存储单元阵列包括包括沿第一方向布置的第一字线和第二字线的字线对，在第一字线和第二字线之间沿第一方向排列的源极线 ，包括沿与第一方向垂直的第二方向布置的第一位线和第二位线的位线对，包括连接到第一字线的栅极的第一存储器单元和分别连接到第二位线的第一和第二区域 线和源极线，并且在第一方向和第二方向之间沿第三方向布置，以及第二存储单元，其包括连接到第二字线的栅极，分别连接到第一位线的第三区域和第二区域 和源极线，并且布置在第三方向。 第一个字线和第二个字线同时被激活。 因此，可以防止在半导体存储单元中的相邻存储单元之间产生的干扰，可以提高半导体存储器件的集成密度，并且可以减少要驱动的字线的数量以使用子字线 结构体。

    Semiconductor memory device including memory cell without capacitor
    6.
    发明申请
    Semiconductor memory device including memory cell without capacitor 失效
    半导体存储器件包括不带电容器的存储单元

    公开(公告)号：US20070195626A1

    公开(公告)日：2007-08-23

    申请号：US11509991

    申请日：2006-08-25

    申请人： Jin-Young Kim ,  Yeong-Taek Lee

    发明人： Jin-Young Kim ,  Yeong-Taek Lee

    IPC分类号： G11C7/02

    CPC分类号： G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2211/4016

    摘要： A semiconductor memory device including a memory cell without a capacitor includes: a memory cell array block including first memory cells connected between a first bit line and first word lines and second memory cells connected between a second bit line and second word lines; and a reference memory cell array block including first reference memory cells connected between a first reference bit line connected to the first bit line and a first reference word line and second reference memory cells connected between a second reference bit line connected to the second bit line and a second reference word line. When the first word lines are selected, the second reference memory cells are selected, and when the second word lines are selected, the first reference memory cells are selected. Thus, each bit line includes a reference memory cell and outputs reference signal from the reference memory cell so that data can be precisely sensed during a read operation.

    摘要翻译： 包括没有电容器的存储单元的半导体存储器件包括：存储单元阵列块，包括连接在第一位线和第一字线之间的第一存储器单元和连接在第二位线和第二字线之间的第二存储器单元; 以及参考存储单元阵列块，其包括连接在与第一位线连接的第一参考位线和第一参考字线之间的第一参考存储单元，以及连接在与第二位线连接的第二参考位线之间的第二参考存储单元;以及 第二个参考字线。 当选择第一字线时，选择第二参考存储单元，并且当选择第二字线时，选择第一参考存储单元。 因此，每个位线包括参考存储单元并输出来自参考存储单元的参考信号，从而可以在读取操作期间精确地感测数据。

    Semiconductor memory device including memory cell without capacitor
    7.
    发明授权
    Semiconductor memory device including memory cell without capacitor 失效
    半导体存储器件包括不带电容器的存储单元

    公开(公告)号：US07388798B2

    公开(公告)日：2008-06-17

    申请号：US11509991

    申请日：2006-08-25

    申请人： Jin-Young Kim ,  Yeong-Taek Lee

    发明人： Jin-Young Kim ,  Yeong-Taek Lee

    IPC分类号： G11C7/02

    CPC分类号： G11C7/14 ,  G11C7/18 ,  G11C11/404 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2211/4016

    摘要： A semiconductor memory device including a memory cell without a capacitor includes: a memory cell array block including first memory cells connected between a first bit line and first word lines and second memory cells connected between a second bit line and second word lines; and a reference memory cell array block including first reference memory cells connected between a first reference bit line connected to the first bit line and a first reference word line and second reference memory cells connected between a second reference bit line connected to the second bit line and a second reference word line. When the first word lines are selected, the second reference memory cells are selected, and when the second word lines are selected, the first reference memory cells are selected. Thus, each bit line includes a reference memory cell and outputs reference signal from the reference memory cell so that data can be precisely sensed during a read operation.

    摘要翻译： 包括没有电容器的存储单元的半导体存储器件包括：存储单元阵列块，包括连接在第一位线和第一字线之间的第一存储器单元和连接在第二位线和第二字线之间的第二存储器单元; 以及参考存储单元阵列块，其包括连接在与第一位线连接的第一参考位线和第一参考字线之间的第一参考存储单元，以及连接在与第二位线连接的第二参考位线之间的第二参考存储单元;以及 第二个参考字线。 当选择第一字线时，选择第二参考存储单元，并且当选择第二字线时，选择第一参考存储单元。 因此，每个位线包括参考存储单元并输出来自参考存储单元的参考信号，从而可以在读取操作期间精确地感测数据。

    Non-volatile memory array and device using erase markers
    9.
    发明授权
    Non-volatile memory array and device using erase markers 有权
    非易失性存储器阵列和使用擦除标记的器件

    公开(公告)号：US08711610B2

    公开(公告)日：2014-04-29

    申请号：US13289277

    申请日：2011-11-04

    申请人： Hui-Kwon Seo ,  Yeong-Taek Lee ,  Yong-Shik Shin

    发明人： Hui-Kwon Seo ,  Yeong-Taek Lee ,  Yong-Shik Shin

    IPC分类号： G11C11/00

    CPC分类号： G11C13/0004 ,  G11C13/004 ,  G11C13/0069

    摘要： A non-volatile memory device, non-volatile memory cell array and related method of operation are disclosed. The non-volatile memory cell array includes a defined data unit stored in a plurality of non-volatile memory cells capable of being electrically overwritten within the non-volatile memory cell array, and an erase marker corresponding to the data unit and indicating whether the data unit is in an erased state or a not-erased state.

    摘要翻译： 公开了一种非易失性存储器件，非易失性存储单元阵列和相关的操作方法。 非易失性存储单元阵列包括存储在能够在非易失性存储单元阵列内被电覆盖的多个非易失性存储单元中的定义数据单元，以及与数据单元对应的擦除标记，并指示数据 单元处于擦除状态或未擦除状态。

    Nonvolatile memory device and program method with improved pass voltage window
    10.
    发明授权
    Nonvolatile memory device and program method with improved pass voltage window 有权
    非易失性存储器件和具有改进的通过电压窗口的程序方法

    公开(公告)号：US08045387B2

    公开(公告)日：2011-10-25

    申请号：US12509612

    申请日：2009-07-27

    申请人： Ki-Tae Park ,  Yeong-Taek Lee ,  Soon-Wook Hwang ,  Young-Wook Jeong

    发明人： Ki-Tae Park ,  Yeong-Taek Lee ,  Soon-Wook Hwang ,  Young-Wook Jeong

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/12 ,  G11C16/0483

    摘要： A flash memory and programming method are disclosed. The flash memory includes a memory cell array having memory cells arranged in a plurality of word lines including a selected word line and a plurality of non-selected word lines and a plurality of bit lines, a high voltage generator generating a program voltage applied to the selected word line, and a pass voltage applied to at least one of the non-selected word lines adjacent to the selected word line, and control logic controlling the generation of the program voltage, such that the program voltage is incrementally increased during a program operation, and generation of the pass voltage, such that the program voltage is incrementally increased.

    摘要翻译： 公开了闪存和编程方法。 闪速存储器包括存储单元阵列，该存储单元阵列具有布置在包括所选择的字线和多个未选择的字线和多个位线的多个字线中的存储器单元，高电压发生器产生施加到该字线的编程电压 所选择的字线和施加到与所选字线相邻的未选择的字线中的至少一个的通过电压，以及控制逻辑，以控制编程电压的产生，使得编程电压在编程操作期间递增地增加 ，并产生通过电压，使得编程电压递增地增加。