公开(公告)号：US20060118835A1

公开(公告)日：2006-06-08

申请号：US10904896

申请日：2004-12-03

申请人： John Ellis-Monaghan ,  Jeffrey Johnson ,  Alain Loiseau

发明人： John Ellis-Monaghan ,  Jeffrey Johnson ,  Alain Loiseau

IPC分类号： H01L31/062

CPC分类号： H01L27/14601 ,  H01L27/14612 ,  H01L27/14689

摘要： A novel Active Pixel Sensor (APS) cell structure and method of manufacture. Particularly, an image sensor APS cell having a predoped transfer gate is formed that avoids the variations of Vt as a result of subsequent manufacturing steps. According to the preferred embodiment of the invention, the image sensor APS cell structure includes a doped p-type pinning layer and an n-type doped gate. There is additionally provided a method of forming the image sensor APS cell having a predoped transfer gate and a doped pinning layer. The predoped transfer gate prevents part of the gate from becoming p-type doped.

摘要翻译： 一种新型的有源像素传感器（APS）单元结构及其制造方法。 特别地，形成具有预定传输门的图像传感器APS单元，其避免了作为后续制造步骤的结果的V变化。 根据本发明的优选实施例，图像传感器APS单元结构包括掺杂的p型钉扎层和n型掺杂栅极。 还提供了一种形成具有预制传输栅极和掺杂钉扎层的图像传感器APS单元的方法。 预制传输门防止栅极的一部分变成p型掺杂。

公开(公告)号：US20070029581A1

公开(公告)日：2007-02-08

申请号：US11161535

申请日：2005-08-08

申请人： James Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jeffrey Johnson ,  Alain Loiseau

发明人： James Adkisson ,  Andres Bryant ,  John Ellis-Monaghan ,  Mark Jaffe ,  Jeffrey Johnson ,  Alain Loiseau

IPC分类号： H01L27/148

CPC分类号： H01L27/14603 ,  H01L27/14609 ,  H01L27/14689 ,  H01L31/035281

摘要： The present invention is a pixel sensor cell and method of making the same. The pixel sensor cell approximately doubles the available signal for a given quanta of light. The device of the present invention utilizes the holes produced by impinging photons in a pixel sensor cell circuit. A pixel sensor cell having reduced complexity includes an n-type collection well region formed beneath a surface of a substrate for collecting electrons generated by electromagnetic radiation impinging on the pixel sensor cell and a p-type collection well region formed beneath the surface of the substrate for collecting holes generated by the impinging photons. A circuit structure having a first input is coupled to the n-type collection well region and a second input is coupled to the p-type collection well region, wherein an output signal of the pixel sensor cell is the magnitude of the difference of a signal of the first input and a signal of the second input.

摘要翻译： 本发明是像素传感器单元及其制造方法。 像素传感器单元对于给定的光量大约使可用信号加倍。 本发明的器件利用通过在像素传感器单元电路中照射光子而产生的空穴。 具有降低的复杂度的像素传感器单元包括形成在基板的表面下面的n型收集阱区域，用于收集由电子辐射照射在像素传感器单元上​​产生的电子以及形成在基板表面下方的p型收集阱区域 用于收集由撞击光子产生的孔。 具有第一输入的电路结构耦合到n型收集阱区域，而第二输入端耦合到p型收集阱区域，其中像素传感器单元的输出信号是信号的差值的大小 的第一输入和第二输入的信号。

公开(公告)号：US20070123042A1

公开(公告)日：2007-05-31

申请号：US11164511

申请日：2005-11-28

申请人： Kern Rim ,  John Ellis-Monaghan ,  Brian Greene ,  William Henson ,  Robert Purtell ,  Clement Wann ,  Horatio Wildman

发明人： Kern Rim ,  John Ellis-Monaghan ,  Brian Greene ,  William Henson ,  Robert Purtell ,  Clement Wann ,  Horatio Wildman

IPC分类号： H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835 ,  H01L21/84

摘要： Methods of fabricating a semiconductor structure including heterogeneous suicides or germanides located in different regions of a semiconductor structure are provided. The heterogeneous suicides or germanides are formed onto a semiconductor layer, a conductive layer or both. In accordance with the present invention, the inventive methods utilize a combination of sequential deposition of different metals and patterning to form different suicides or germanides in different regions of a semiconductor chip. The method includes providing a Si-containing or Ge layer having at least a first region and a second region; forming a first silicide or germanide on one of the first or second regions; and forming a second silicide or germanide that is compositionally different from the first silicide or germanide on the other region not including the first silicide or germanide, wherein the steps of forming the first and second suicides or germanides are performed sequentially or in a single step.

摘要翻译： 提供了制造半导体结构的方法，其包括位于半导体结构的不同区域中的异质自杀或锗化物。 异质自杀或锗化物形成在半导体层，导电层或两者上。 根据本发明，本发明的方法利用不同金属的顺序沉积和图案化的组合以在半导体芯片的不同区域中形成不同的自杀或锗化物。 该方法包括提供具有至少第一区域和第二区域的含Si或Ge层; 在所述第一或第二区域之一上形成第一硅化物或锗化物; 并且在不包括第一硅化物或锗化锗的另一区域上形成与第一硅化物或锗化物在组成上不同的第二硅化物或锗化物，其中形成第一和第二硅化物或锗化物的步骤依次进行或单步进行。

公开(公告)号：US07217968B2

公开(公告)日：2007-05-15

申请号：US10905097

申请日：2004-12-15

申请人： James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

发明人： James W. Adkisson ,  John Ellis-Monaghan ,  Mark D. Jaffe ,  Jerome B. Lasky

IPC分类号： H01L31/062

CPC分类号： H01L27/14603 ,  H01L27/14601 ,  H01L27/14689 ,  H01L29/66621

摘要： A novel image sensor cell structure and method of manufacture. The imaging sensor comprises a substrate, a gate comprising a dielectric layer and gate conductor formed on the dielectric layer, a collection well layer of a first conductivity type formed below a surface of the substrate adjacent a first side of the gate conductor, a pinning layer of a second conductivity type formed atop the collection well at the substrate surface, and a diffusion region of a first conductivity type formed adjacent a second side of the gate conductor, the gate conductor forming a channel region between the collection well layer and the diffusion region. Part of the gate conductor bottom is recessed below the surface of the substrate. Preferably, a portion of the gate conductor is recessed at or below a bottom surface of the pinning layer to a depth such that the collection well intersects the channel region.

摘要翻译： 一种新颖的图像传感器单元结构及其制造方法。 成像传感器包括基板，包括电介质层和形成在电介质层上的栅极导体的栅极，形成在与栅极导体的第一侧相邻的基板的表面下面的第一导电类型的收集阱层，钉扎层 在基板表面上形成在集合阱顶部的第二导电类型的第一导电类型的扩散区和在栅极导体的第二侧附近形成的第一导电类型的扩散区，栅极导体在集电阱层和扩散区之间形成沟道区 。 栅极导体底部的一部分凹陷在基板的表面下方。 优选地，栅极导体的一部分在钉扎层的底表面处或下方凹陷到使得收集阱与沟道区相交的深度。

公开(公告)号：US20060286778A1

公开(公告)日：2006-12-21

申请号：US11160365

申请日：2005-06-21

申请人： Brent Anderson ,  John Ellis-Monaghan ,  Alain Loiseau ,  Kirk Peterson

发明人： Brent Anderson ,  John Ellis-Monaghan ,  Alain Loiseau ,  Kirk Peterson

IPC分类号： H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/8252

摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.

摘要翻译： 公开了制造双取向晶片的方法。 在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。 沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。 形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。 另外的隔离结构形成在沟槽内和半导体层内的硅材料内。 对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。 所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

公开(公告)号：US20060121662A1

公开(公告)日：2006-06-08

申请号：US10904884

申请日：2004-12-02

申请人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

发明人： Sunfei Fang ,  Cyril Cabral ,  Chester Dziobkowski ,  John Ellis-Monaghan ,  Christian Lavoie ,  Zhijiong Luo ,  James Nakos ,  An Steegen ,  Clement Wann

IPC分类号： H01L21/8238 ,  H01L21/3205 ,  H01L21/44

CPC分类号： H01L21/28518 ,  H01L21/823814 ,  H01L21/823835

摘要： A method of fabricating a complementary metal oxide semiconductor (CMOS) device, wherein the method comprises forming a first well region in a semiconductor substrate for accommodation of a first type semiconductor device; forming a second well region in the semiconductor substrate for accommodation of a second type semiconductor device; shielding the first type semiconductor device with a mask; depositing a first metal layer over the second type semiconductor device; performing a first salicide formation on the second type semiconductor device; removing the mask; depositing a second metal layer over the first and second type semiconductor devices; and performing a second salicide formation on the first type semiconductor device. The method requires only one pattern level and it eliminates pattern overlay as it also simplifies the processes to form different silicide material over different devices.

公开(公告)号：US09543356B2

公开(公告)日：2017-01-10

申请号：US12538194

申请日：2009-08-10

申请人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  John Ellis-Monaghan ,  Richard Rassel

发明人： Jeffrey P. Gambino ,  Mark D. Jaffe ,  John Ellis-Monaghan ,  Richard Rassel

IPC分类号： H01L27/148 ,  H01L27/146

CPC分类号： H01L27/14689 ,  H01L27/14609 ,  H01L27/14623 ,  H01L27/1464

摘要： CMOS image sensor pixel sensor cells, methods for fabricating the pixel sensor cells and design structures for fabricating the pixel sensor cells are designed to allow for back side illumination in global shutter mode by providing light shielding from back side illumination of at least one transistor within the pixel sensor cells. In a first particular generalized embodiment, a light shielding layer is located and formed interposed between a first semiconductor layer that includes a photoactive region and a second semiconductor layer that includes the at least a second transistor, or a floating diffusion, that is shielded by the light blocking layer. In a second generalized embodiment, a thin film transistor and a metal-insulator-metal capacitor are used in place of a floating diffusion, and located shielded in a dielectric isolated metallization stack over a carrier substrate.

摘要翻译： CMOS图像传感器像素传感器单元，用于制造像素传感器单元的方法和用于制造像素传感器单元的设计结构被设计成允许在全局快门模式中进行背面照明，通过提供来自至少一个晶体管的背侧照明的光屏蔽 像素传感器单元。 在第一特定广义实施例中，遮光层位于包括光活性区的第一半导体层和包括至少第二晶体管的第二半导体层之间并形成，或者浮置扩散部被屏蔽 遮光层。 在第二广义实施例中，使用薄膜晶体管和金属 - 绝缘体 - 金属电容器来代替浮动扩散，并且被定位在载体衬底上的介电隔离金属化堆叠中。

公开(公告)号：US20080096370A1

公开(公告)日：2008-04-24

申请号：US11955436

申请日：2007-12-13

申请人： Brent Anderson ,  John Ellis-Monaghan ,  Alain Loiseau ,  Kirk Peterson

发明人： Brent Anderson ,  John Ellis-Monaghan ,  Alain Loiseau ,  Kirk Peterson

IPC分类号： H01L21/20

CPC分类号： H01L21/823807 ,  H01L21/823878 ,  H01L21/8252

摘要： Disclosed is a method of manufacturing dual orientation wafers. A trench is formed in a multi-layer wafer to a silicon substrate with a first crystalline orientation. The trench is filled with a silicon material (e.g., amorphous silicon or polysilicon trench). Isolation structures are formed to isolate the silicon material in the trench from a semiconductor layer with a second crystalline orientation. Additional isolation structures are formed within the silicon material in the trench and within the semiconductor layer. A patterned amorphization process is performed on the silicon material in the trench and followed by a recrystallization anneal such that the silicon material in the trench recrystallizes with the same crystalline orientation as the silicon substrate. The resulting structure is a semiconductor wafer with isolated semiconductor areas on the same plane having different crystalline orientations as well as isolated sections within each semiconductor area for device formation.

摘要翻译： 公开了制造双取向晶片的方法。 在多层晶片中形成具有第一晶体取向的硅衬底的沟槽。 沟槽填充有硅材料（例如，非晶硅或多晶硅沟槽）。 形成隔离结构以将沟槽中的硅材料与具有第二晶体取向的半导体层隔离。 另外的隔离结构形成在沟槽内和半导体层内的硅材料内。 对沟槽中的硅材料进行图案化非晶化处理，然后进行再结晶退火，使得沟槽中的硅材料以与硅衬底相同的结晶取向重结晶。 所得到的结构是在具有不同晶体取向的同一平面上的隔离半导体区域以及用于器件形成的每个半导体区域内的隔离部分的半导体晶片。

公开(公告)号：US20070235780A1

公开(公告)日：2007-10-11

申请号：US11765485

申请日：2007-06-20

申请人： John Ellis-Monaghan ,  Mark Jaffe ,  Alain Loiseau

发明人： John Ellis-Monaghan ,  Mark Jaffe ,  Alain Loiseau

IPC分类号： H01L31/0352

CPC分类号： H01L27/14643 ,  H01L27/14603 ,  H01L27/14609 ,  H01L27/14679

摘要： An imaging circuit, an imaging sensor, and a method of imaging. The imaging cell circuit including one or more imaging cell circuits, each imaging cell circuit comprising: a transistor having a floating body for holding charge generated in the floating body in response to exposure of the floating body to electromagnetic radiation; means for biasing the transistor wherein an output of the transistor is responsive to the electromagnetic radiation; and means for selectively connecting the floating body to a reset voltage supply.

摘要翻译： 成像电路，成像传感器和成像方法。 所述成像单元电路包括一个或多个成像单元电路，每个成像单元电路包括：晶体管，具有浮动体，用于响应于浮体暴露于电磁辐射而保持在浮体中产生的电荷; 用于偏置晶体管的装置，其中晶体管的输出响应于电磁辐射; 以及用于选择性地将浮动体连接到复位电压源的装置。

公开(公告)号：US20070187734A1

公开(公告)日：2007-08-16

申请号：US11276085

申请日：2006-02-14

申请人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Dale Pearson ,  Dennis Rogers

发明人： James Adkisson ,  John Ellis-Monaghan ,  Mark Jaffe ,  Dale Pearson ,  Dennis Rogers

IPC分类号： H01L31/062

CPC分类号： H01L27/14643 ,  H01L27/1463 ,  H01L27/14689 ,  H01L31/035281

摘要： A pixel sensor cell having a semiconductor substrate having a surface; a photosensitive element formed in a substrate having a non-laterally disposed charge collection region entirely isolated from a physical boundary including the substrate surface. The photosensitive element comprises a trench having sidewalls formed in the substrate of a first conductivity type material; a first doped layer of a second conductivity type material formed adjacent to at least one of the sidewalls; and a second doped layer of the first conductivity type material formed between the first doped layer and the at least one trench sidewall and formed at a surface of the substrate, the second doped layer isolating the first doped layer from the at least one trench sidewall and the substrate surface. In a further embodiment, an additional photosensitive element is provided that includes a laterally disposed charge collection region that contacts the non-laterally disposed charge collection region of the photosensitive element and underlies the doped layer formed at the substrate surface.

摘要翻译： 一种像素传感器单元，具有具有表面的半导体衬底; 形成在具有与包括基板表面的物理边界完全隔离的非横向布置的电荷收集区域的基板中的感光元件。 感光元件包括具有形成在第一导电类型材料的衬底中的侧壁的沟槽; 与所述侧壁中的至少一个相邻形成的第二导电类型材料的第一掺杂层; 以及形成在所述第一掺杂层和所述至少一个沟槽侧壁之间且形成在所述衬底的表面处的所述第一导电类型材料的第二掺杂层，所述第二掺杂层将所述第一掺杂层与所述至少一个沟槽侧壁隔离， 基材表面。 在另一个实施例中，提供附加的光敏元件，其包括横向设置的电荷收集区域，其接触感光元件的非横向设置的电荷收集区域，并且位于形成在基底表面处的掺杂层的下方。