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公开(公告)号：US08819602B2
公开(公告)日：2014-08-26
申请号：US13548460
申请日：2012-07-13
申请人： Georg Georgakos
发明人： Georg Georgakos
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , Y02T10/82
摘要： Structures of a circuit are identified. Voltages are propagated to the identified structures. Additionally, internal node voltages for the identified structures are obtained. Asymmetrical operating conditions are identified.
摘要翻译： 识别电路的结构。 电压被传播到所识别的结构。 另外，获得所识别的结构的内部节点电压。 识别非对称操作条件。
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公开(公告)号：US20140019928A1
公开(公告)日：2014-01-16
申请号：US13548460
申请日：2012-07-13
申请人： Georg Georgakos
发明人： Georg Georgakos
IPC分类号： G06F17/50
CPC分类号： G06F17/5081 , Y02T10/82
摘要： Structures of a circuit are identified. Voltages are propagated to the identified structures. Additionally, internal node voltages for the identified structures are obtained. Asymmetrical operating conditions are identified.
摘要翻译： 识别电路的结构。 电压被传播到所识别的结构。 另外，获得所识别的结构的内部节点电压。 识别非对称操作条件。
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公开(公告)号：US07453125B1
公开(公告)日：2008-11-18
申请号：US11739420
申请日：2007-04-24
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L29/66795 , H01L29/785
摘要： A multiple gate field-effect transistor is built from an overlapping mesh assembly. The assembly comprises a first layer comprising a semiconductor material formed into at least one fin, at least one source, and at least one drain. The first layer comprises a portion of a first mesh, electrically separated from the rest of the mesh. Similarly, a second layer is formed over the first layer and electrically isolated from the first layer, the second layer being electrically conductive and comprising a gate for the at least on fin of the transistor. The second layer comprises a portion of a second mesh offset from the first mesh and overlapping the first mesh, the second layer of the MuGFET device electrically separated from the rest of the second mesh.
摘要翻译： 多栅极场效应晶体管由重叠的网格组件构成。 该组件包括第一层，该第一层包括形成至少一个翅片，至少一个源极和至少一个漏极的半导体材料。 第一层包括与网的其余部分电分离的第一网的一部分。 类似地，第二层形成在第一层上并与第一层电绝缘，第二层是导电的，并且包括晶体管的至少一个鳍上的栅极。 第二层包括从第一网格偏移并与第一网格重叠的第二网格的一部分，MuGFET装置的第二层与第二网格的其余部分电分离。
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公开(公告)号：US20050163277A1
公开(公告)日：2005-07-28
申请号：US11004047
申请日：2004-12-03
IPC分类号： G11C8/04 , G11C19/00 , G11C19/28 , H03K19/177
CPC分类号： H03K19/17748 , G11C8/04 , G11C19/00 , G11C19/28 , H03K19/177
摘要： Shift register for safely providing a configuration bit The invention relates to a shift register cell (1-i, 100-i) for safely providing a configuration bit (6-i) having a master latch (8-i) which can be connected to a serial data input (2-i) on the shift register cell (1-i, 100-i) for the purpose of buffer-storing a data bit (3-i); a first slave latch (10-i) which can be connected to the master latch (8-i) for the purpose of buffer-storing the data bit; at least one second slave latch (12-i) which can be connected to the master latch (8-i) for the purpose of buffer-storing the data bit, and having an evaluation logic unit (13-i) which outputs the configuration bit (6-i) on the basis of the data bits which are buffer-stored in the master latch (8-i) and in the slave latches (10-i, 12-i). In addition, the invention provides a shift register (17) for safely providing configuration bits (6-1, . . . 6-N) which has a plurality of inventive shift register cells (1-1, . . . 1-N, 100-1, . . . 100-N) which are connected in series to form a shift register chain (1, 100).
摘要翻译： 用于安全地提供配置位的移位寄存器技术领域本发明涉及一种用于安全地提供具有主锁存器（8-i）的配置位（6-i）的移位寄存器单元（1-i，100i），其可以连接到 用于缓冲存储数据位（3-i）的移位寄存器单元（1 -i，100-i）上的串行数据输入（2-i）; 第一从锁存器（10-i），其可以连接到主锁存器（8-i），用于缓冲存储数据位; 至少一个第二从锁存器（12-i），其可以连接到主锁存器（8-i），用于缓冲存储数据位，并具有输出配置的评估逻辑单元（13-i） 基于缓冲存储在主锁存器（8-i）和从锁存器（10 -i-12-i）中的数据位来执行位（6-i）。 另外，本发明提供了一种用于安全地提供配置位（6-1，...，6-N）的移位寄存器（17），其具有多个本发明的移位寄存器单元（1至1，...， 100 -1，...，100 -N），其串联连接以形成移位寄存器链（1,100）。
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15.发明授权Nonvolatile NOR two-transistor semiconductor memory cell and associated NOR semiconductor memory device and method for the fabrication thereof 失效非易失性NOR双晶体管半导体存储器单元及其相关的NOR半导体存储器件及其制造方法公开(公告)号：US06844603B2
公开(公告)日：2005-01-18
申请号：US10314177
申请日：2002-12-06
CPC分类号： G11C16/0433
摘要： The invention relates to a nonvolatile NOR two-transistor semiconductor memory cell, an associated semiconductor memory device and a method for the fabrication thereof, in which one-transistor memory cells are located in an active region formed in annular fashion and are driven via associated word lines. In this case, the source regions of the one-transistor memory cells are connected via a source line, while the drain regions are connected via corresponding drain lines. A reduced space requirement for the two-transistor semiconductor memory cell is obtained in particular on account of the annular structure of the active regions.
摘要翻译： 本发明涉及一种非易失性NOR双晶体管半导体存储单元，一种相关的半导体存储器件及其制造方法，其中一晶体管存储单元位于以环形形式形成的有源区中，并通过相关字驱动 线条。 在这种情况下，单晶体管存储单元的源极区域经由源极线连接，而漏极区域经由相应的漏极线连接。 特别是由于活性区域的环形结构，获得了双晶体管半导体存储单元的空间要求减小。
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16.发明授权Circuit configuration for a programmable nonvolatile memory and method for operating the circuit configuration 有权用于可编程非易失性存储器的电路配置和用于操作电路配置的方法
公开(公告)号：US5946249A
公开(公告)日：1999-08-31
申请号：US145212
申请日：1998-08-31
申请人： Georg Georgakos , Thomas Kern , Diether Sommer , Thomas Zettler
发明人： Georg Georgakos , Thomas Kern , Diether Sommer , Thomas Zettler
摘要： A circuit configuration for a programmable nonvolatile memory having memory cells organized in rows and columns, includes a programming circuit which contains a first device for testing purposes that applies a programming current to a first predetermined number of memory cells in parallel for a first predetermined time period. During a second predetermined time period, the device thereupon connects a second predetermined number, which is greater than the first number, in parallel an applies the programming current to them. A method is provided for operating the circuit configuration.
摘要翻译： 一种用于具有以行和列组织的存储器单元的可编程非易失性存储器的电路配置，包括编程电路，其包含用于测试目的的第一设备，用于将编程电流并行地施加到第一预定数量的存储器单元达第一预定时间段 。 在第二预定时间段期间，该装置在其上并联连接大于第一数目的第二预定数量并行编程电流。 提供了一种用于操作电路配置的方法。
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公开(公告)号：US20120240014A1
公开(公告)日：2012-09-20
申请号：US13047090
申请日：2011-03-14
申请人： Georg Georgakos , Michael Gössel , Anton Huber
发明人： Georg Georgakos , Michael Gössel , Anton Huber
CPC分类号： G11C11/419 , G06F11/1032 , G11C2029/0411
摘要： One embodiment of the present invention relates to an error tolerant memory circuit having a low hardware overhead that can tolerate both single volatile soft errors and permanent errors. In one embodiment, the method and apparatus comprise a memory circuit having a plurality of memory element pairs, respectively having two memory storage elements configured to store a data unit. One or more parity generation circuits are configured to calculate a first parity bit from data written to the plurality of memory element pairs (e.g., the two memory storage elements) and a second parity bit from data read from one of the two memory storage elements in the plurality of memory element pairs. Based upon the calculated first and second parity bits, the memory circuit chooses to selectively output data from memory storage elements not known to contain an error.
摘要翻译： 本发明的一个实施例涉及具有低硬件开销的容错存储器电路，其可容忍单个易失性软错误和永久错误。 在一个实施例中，该方法和装置包括具有多个存储元件对的存储器电路，其分别具有被配置为存储数据单元的两个存储器存储元件。 一个或多个奇偶校验生成电路被配置为从从两个存储器元件对（例如，两个存储器元件）中写入的数据中计算第一奇偶校验位，并且从位于 多个存储元件对。 基于所计算的第一和第二奇偶校验位，存储器电路选择选择性地从不知道包含错误的存储器存储元件输出数据。
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公开(公告)号：US20080265290A1
公开(公告)日：2008-10-30
申请号：US11739420
申请日：2007-04-24
IPC分类号： H01L29/76
CPC分类号： H01L21/823437 , H01L21/823412 , H01L21/823431 , H01L29/66795 , H01L29/785
摘要： A multiple gate field-effect transistor is built from an overlapping mesh assembly. The assembly comprises a first layer comprising a semiconductor material formed into at least one fin, a least one source, and at least one drain. The first layer comprises a portion of a first mesh, electrically separated from the rest of the mesh. Similarly, a second layer is formed over the first layer and electrically isolated from the first layer, the second layer being electrically conductive and comprising a gate for the at least one fin of the transistor. The second layer comprises a portion of a second mesh offset from the first mesh and overlapping the first mesh, the second layer of the MuGFET device electrically separated from the rest of the second mesh.
摘要翻译： 多栅极场效应晶体管由重叠的网格组件构成。 该组件包括第一层，该第一层包括形成至少一个鳍，至少一个源和至少一个漏极的半导体材料。 第一层包括与网的其余部分电分离的第一网的一部分。 类似地，第二层形成在第一层上并与第一层电绝缘，第二层是导电的并且包括晶体管的至少一个鳍的栅极。 第二层包括从第一网格偏移并与第一网格重叠的第二网格的一部分，MuGFET装置的第二层与第二网格的其余部分电分离。
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公开(公告)号：US06212102B1
公开(公告)日：2001-04-03
申请号：US09250364
申请日：1999-02-12
申请人： Georg Georgakos , Martin Bloch , Kai Kasprick , Thomas Kern , Jürgen Peter , Thomas Piorek
发明人： Georg Georgakos , Martin Bloch , Kai Kasprick , Thomas Kern , Jürgen Peter , Thomas Piorek
IPC分类号： G11C1604
CPC分类号： G11C16/3427 , G11C16/0433 , G11C16/10
摘要： An EEPROM with two-transistor memory cells with source-side selection, and a method for triggering such a EEPROM are described. The EEPROM and the method are distinguished in that the programming voltage required to program a memory cell is delivered via a source line. As a result the EEPROM can be protected in a simple way against unintended loss of the data stored in it.
摘要翻译： 描述了具有源侧选择的双晶体管存储单元的EEPROM和用于触发这种EEPROM的方法。 EEPROM和方法的区别在于，通过源极线传送编程存储器单元所需的编程电压。 因此，EEPROM可以以简单的方式进行保护，以防止存储在其中的数据的意外丢失。
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公开(公告)号：US08847604B2
公开(公告)日：2014-09-30
申请号：US13298316
申请日：2011-11-17
IPC分类号： G01R31/02 , G01R23/14 , H03D13/00 , G01R31/3181 , G01R31/30 , G01R31/317 , G01R31/28
CPC分类号： G01R31/3181 , G01R31/2856 , G01R31/3016 , G01R31/31703
摘要： Implementations are presented herein that include a test circuit and a reference circuit.
摘要翻译： 本文给出了包括测试电路和参考电路的实现。
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