公开(公告)号：US20120262323A1

公开(公告)日：2012-10-18

申请号：US13333983

申请日：2011-12-21

申请人： Taek-Sang SONG ,  Dae-Han Kwon

发明人： Taek-Sang SONG ,  Dae-Han Kwon

IPC分类号： H04L17/02

CPC分类号： H03K5/2481 ,  H03K19/0027 ,  H03K19/0948

摘要： A buffer control circuit includes a current supply unit configured to supply current and adjust the current in response to codes, an amplifying buffer configured to operate using the current and output a value obtained by comparing a reference potential and the reference potential, a second buffer configured to buffer an output of the first buffer, and a code generation unit configured to generate the codes in response to an output of the second buffer.

摘要翻译： 缓冲器控制电路包括：电流供给单元，被配置为响应于代码提供电流并调节电流;放大缓冲器，被配置为使用电流进行操作并输出通过比较参考电位和参考电位获得的值;配置的第二缓冲器 以缓冲第一缓冲器的输出;以及代码生成单元，被配置为响应于第二缓冲器的输出而生成代码。

公开(公告)号：US08253465B2

公开(公告)日：2012-08-28

申请号：US13186366

申请日：2011-07-19

申请人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Dae-Kun Yoon ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K3/00 ,  H03K5/13 ,  H03H11/16

CPC分类号： G11C7/22 ,  G11C7/1066 ,  G11C7/1072 ,  G11C7/222 ,  H03L7/0814

摘要： A semiconductor memory device includes an edge detector configured to receive two pairs of complementary clocks to detect edges of the clocks, a comparator configured to compare output signals of the edge detector to detect whether clocks of the same pair have a phase difference of 180 degrees and detect whether clocks of different pairs have a phase difference of 90 degrees, a control signal generator configured to generate a control signal for controlling phases of the clocks according to an output signal of the comparator, and a phase corrector configured to correct phases of the clocks in response to the control signal.

摘要翻译： 半导体存储器件包括边缘检测器，被配置为接收两对互补时钟以检测时钟的边沿;比较器，被配置为比较边缘检测器的输出信号，以检测同一对的时钟是否具有180度的相位差;以及 检测不同对的时钟是否具有90度的相位差，控制信号发生器被配置为根据比较器的输出信号产生用于控制时钟相位的控制信号;以及相位校正器，被配置为校正时钟的相位 响应于控制信号。

公开(公告)号：US07961026B2

公开(公告)日：2011-06-14

申请号：US12003676

申请日：2007-12-31

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03H11/26

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

摘要翻译： 通过根据PVT的条件控制延迟单元的延迟时间来产生内部时钟的锁相环，从而提高内部时钟的抖动特性。 延迟单元包括响应于控制电压控制第一和第二电流的第一电流控制器，以及响应频率范围选择信号控制第一和第二电流的第二电流控制器。 锁相环包括用于将参考时钟与反馈时钟进行比较的相位比较器，用于产生对应于相位比较器的输出的控制电压的控制电压发生器和用于产生具有频率的内部时钟的压控振荡器 响应于控制电压和一个或多个频率范围控制信号，其中使用内部时钟产生反馈时钟。

公开(公告)号：US07884647B2

公开(公告)日：2011-02-08

申请号：US12326990

申请日：2008-12-03

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： H03K19/0175

CPC分类号： H03K19/018528

摘要： There is provided an output driver, which includes a pre-driver configured to generate a main driving control signal in response to a data signal, a main driver configured to drive an output terminal in response to the main driving control signal, an auxiliary driving control signal generator configured to generate an auxiliary driving control signal having an activation interval corresponding to the data signal and an interval control signal, and an auxiliary driver configured to drive the output terminal in response to the auxiliary driving control signal.

摘要翻译： 提供了一种输出驱动器，其包括配置为响应于数据信号产生主驱动控制信号的预驱动器，配置成响应于主驱动控制信号驱动输出端的主驱动器，辅助驱动控制 信号发生器，其被配置为产生具有与数据信号和间隔控制信号对应的激活间隔的辅助驱动控制信号，以及配置为响应于辅助驱动控制信号来驱动输出端子的辅助驱动器。

公开(公告)号：US20090273493A1

公开(公告)日：2009-11-05

申请号：US12215772

申请日：2008-06-30

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Chang-Kyu Choi ,  Taek-Sang Song

IPC分类号： H03M9/00

CPC分类号： H03M9/00

摘要： A parallel-to-serial converter includes a data input unit configured to receive a plurality of parallel data by using a plurality of clock signals having different phases, and a parallel-to-serial conversion unit configured to sequentially select and output an output signal of the data input unit by using a plurality of clock signals having a predetermined phase difference from the plurality of clock signals used in the data input unit.

摘要翻译： 并行转换器包括：数据输入单元，被配置为通过使用具有不同相位的多个时钟信号来接收多个并行数据;以及并行到串行转换单元，被配置为顺序地选择和输出 数据输入单元通过使用与数据输入单元中使用的多个时钟信号具有预定相位差的多个时钟信号。

公开(公告)号：US20090121701A1

公开(公告)日：2009-05-14

申请号：US12266693

申请日：2008-11-07

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G05F3/16

CPC分类号： G05F3/30 ,  G11C5/147

摘要： A bandgap reference generating circuit includes an operational amplifier configured to generate a bandgap reference voltage; and a gain controller configured to control a gain of the operational amplifier with different values in a normal mode and a low power mode.

摘要翻译： 带隙参考产生电路包括：运算放大器，被配置为产生带隙参考电压; 以及增益控制器，被配置为在正常模式和低功率模式下以不同的值来控制运算放大器的增益。

公开(公告)号：US08867698B2

公开(公告)日：2014-10-21

申请号：US13620564

申请日：2012-09-14

申请人： Dae-Han Kwon ,  Yong-Ju Kim ,  Jae-Il Kim ,  Taek-Sang Song

发明人： Dae-Han Kwon ,  Yong-Ju Kim ,  Jae-Il Kim ,  Taek-Sang Song

IPC分类号： H03K21/38

CPC分类号： H03K21/38 ,  H03K21/023

摘要： A counting circuit includes: a clock division unit configured to divide a reference clock signal at a preset division ratio and generate a divided clock signal, a counting unit configured to count the divided clock signal, and a counting control unit configured to enable the counting unit during an enable period corresponding to the division ratio.

摘要翻译： 计数电路包括：时钟分割单元，被配置为以预设的分频比划分参考时钟信号并产生分频时钟信号;计数单元，被配置为对分频时钟信号进行计数;计数控制单元，被配置为使计数单元 在对应于分频比的使能期间。

公开(公告)号：US08570109B2

公开(公告)日：2013-10-29

申请号：US13081119

申请日：2011-04-06

申请人： Taek-Sang Song ,  Dae-Han Kwon ,  Dae-Kun Yoon

发明人： Taek-Sang Song ,  Dae-Han Kwon ,  Dae-Kun Yoon

IPC分类号： H03K3/03

CPC分类号： H03K3/0322 ,  H03K23/542

摘要： A ring oscillator including a plurality of buffer units, each of which has a cross-coupled structure, for generating clock signals using a bias voltage having a predetermined voltage level applied thereto, wherein the clock signals have a swing width corresponding to the bias voltage.

摘要翻译： 一种环形振荡器，包括多个缓冲单元，每个缓冲单元具有交叉耦合结构，用于使用施加有预定电压电平的偏置电压来产生时钟信号，其中时钟信号具有对应于偏置电压的摆幅宽度。

公开(公告)号：US08072254B2

公开(公告)日：2011-12-06

申请号：US13102938

申请日：2011-05-06

申请人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

发明人： Taek-Sang Song ,  Kyung-Hoon Kim ,  Dae-Han Kwon

IPC分类号： H03H11/26

CPC分类号： H03L7/0995 ,  H03K3/0322 ,  H03K5/133 ,  H03K2005/00208 ,  H03K2005/00234 ,  H03L2207/06

摘要： A phase locked loop that generates an internal clock by controlling a delay time of a delay cell according to conditions of PVT, thereby improving a jitter characteristic of the internal clock. The delay cell includes a first current controller for controlling first and second currents in response to a control voltage, and a second current controller for controlling the first and second currents in response to frequency range selection signals. The phase locked loop includes a phase comparator for comparing a reference clock with a feedback clock, a control voltage generator for generating a control voltage corresponding to an output of the phase comparator, and a voltage controlled oscillator for generating an internal clock having a frequency in response to the control voltage and one or more frequency range control signals, wherein the feedback clock is generated using the internal clock.

公开(公告)号：US07834611B2

公开(公告)日：2010-11-16

申请号：US12266693

申请日：2008-11-07

申请人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

发明人： Kyung-Hoon Kim ,  Dae-Han Kwon ,  Taek-Sang Song

IPC分类号： G05F3/16 ,  G05F1/10

CPC分类号： G05F3/30 ,  G11C5/147

摘要： A bandgap reference generating circuit includes an operational amplifier configured to generate a bandgap reference voltage; and a gain controller configured to control a gain of the operational amplifier with different values in a normal mode and a low power mode.

摘要翻译： 带隙参考产生电路包括：运算放大器，被配置为产生带隙参考电压; 以及增益控制器，被配置为在正常模式和低功率模式下以不同的值来控制运算放大器的增益。