公开(公告)号：US06903423B2

公开(公告)日：2005-06-07

申请号：US10843318

申请日：2004-05-12

申请人： Helmut Fischer ,  Jens Egerer

发明人： Helmut Fischer ,  Jens Egerer

IPC分类号： G11C5/14 ,  G11C11/407 ,  G11C29/00 ,  G11C29/02 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062 ,  H01L31/113 ,  H01L31/119

CPC分类号： G11C29/02 ,  G11C2029/5006

摘要： An integrated semiconductor memory can include a plurality of subcircuit blocks arranged on nonoverlapping area sections. The subcircuit blocks each have a block supply line and a block ground line, which supply individual switching elements of the subcircuit blocks with a voltage. Each block supply line and block ground line is connected to a chip supply line and a chip ground line, which run outside the area sections of the subcircuit blocks. At least one connection between the chip supply line and the block supply line of at least one subcircuit block or between the chip ground line and the block ground line of at least one subcircuit block can be isolated by a switching device. Furthermore, a method for reducing leakage currents in a semiconductor memory, which, depending on the operating state of the semiconductor memory, isolates or connects individual subcircuit blocks of the semiconductor memory from or to a voltage supply.

摘要翻译： 集成半导体存储器可以包括布置在非重叠区域部分上的多个子电路块。 每个子电路块具有块供电线和块接地线，其为电路中的各个电路块的各个开关元件提供电压。 每个块供电线和块接地线连接到芯片供电线和芯片接地线，其在子电路块的区域外延伸。 至少一个子电路块的芯片供给线和块供应线之间或至少一个子电路块的芯片接地线和块接地线之间的至少一个连接可以由开关器件隔离。 此外，一种减少半导体存储器中漏电流的方法，其取决于半导体存储器的工作状态，将半导体存储器的各个子电路块与电压源隔离或连接。

公开(公告)号：US06744304B2

公开(公告)日：2004-06-01

申请号：US10234078

申请日：2002-09-03

申请人： Jens Egerer ,  Heiko Fibranz ,  Eckehard Plaettner

发明人： Jens Egerer ,  Heiko Fibranz ,  Eckehard Plaettner

IPC分类号： G05F322

CPC分类号： G05F3/225

摘要： An electronic circuit for generating an output voltage has a defined temperature dependence, a bandgap circuit for generating a defined temperature-constant voltage and a temperature-dependent current with a defined temperature dependence, and a conversion circuit for generating the output voltage from the temperature-dependent current and the temperature-constant voltage. The conversion circuit has a first resistor at whose first terminal the temperature-constant voltage is applied, and whose second terminal is connected to a first terminal of a second resistor. The second terminal of the second resistor is connected to a supply voltage potential, and a first terminal of a third resistor is connected to the second terminal of the first resistor. The temperature-dependent current is supplied to a second terminal of the third resistor, and it being possible to tap the output voltage at the second terminal of the third resistor.

摘要翻译： 用于产生输出电压的电子电路具有确定的温度依赖性，用于产生限定的温度恒定电压的带隙电路和具有确定的温度依赖性的依赖于温度的电流，以及用于从温度依赖性产生输出电压的转换电路， 依赖电流和温度恒定电压。 转换电路具有第一电阻器，其第一端子施加温度恒定电压，并且其第二端子连接到第二电阻器的第一端子。 第二电阻器的第二端子连接到电源电压电位，第三电阻器的第一端子连接到第一电阻器的第二端子。 温度相关电流被提供给第三电阻器的第二端子，并且可以抽出第三电阻器的第二端子处的输出电压。

公开(公告)号：US06724240B2

公开(公告)日：2004-04-20

申请号：US10210665

申请日：2002-08-01

申请人： Jens Egerer

发明人： Jens Egerer

IPC分类号： G05F110

CPC分类号： H02M3/073 ,  H02M2003/075

摘要： A method and an integrated circuit for boosting a voltage are disclosed. A two-stage charge pump is used and has switches and capacitors. Known charges pumps can be single-stage or multi-stage and can achieve only a doubling of the input voltage in practice, depending on the configuration of the switches and capacitors and whereby each stage is provided with a separate drive. An improved two-stage charge pump can triple the input voltage and is advantageously achieved. N-type field effect transistors that are embedded in the substrate of an integrated circuit are utilized as the switches. It is further provided that a second series pass transistor is driven at its bulk terminal and/or its gate by a capacitor and a level shifter. This advantageously obviates the need to expand the width of the additional series pass transistor.

摘要翻译： 公开了一种用于升压电压的方法和集成电路。 使用两级电荷泵，并具有开关和电容器。 已知的电荷泵可以是单级的或多级的，并且在实践中可以仅实现输入电压的倍增，这取决于开关和电容器的配置，并且由此每个级设置有单独的驱动器。 改进的两级电荷泵可以使输入电压加倍，并且有利地实现。 嵌入在集成电路的基板中的N型场效应晶体管被用作开关。 进一步地，第二串联传输晶体管在其体积端子和/或其栅极通过电容器和电平转换器驱动。 这有利地避免了扩大附加串联晶体管的宽度的需要。

公开(公告)号：US20090268532A1

公开(公告)日：2009-10-29

申请号：US12110859

申请日：2008-04-28

申请人： Luca De Ambroggi ,  Jens Egerer ,  Peter Schroegmeier

发明人： Luca De Ambroggi ,  Jens Egerer ,  Peter Schroegmeier

IPC分类号： G11C7/00

CPC分类号： G11C7/22 ,  G06F12/0238 ,  G06F12/0246 ,  G06F2212/1004 ,  G06F2212/7202 ,  G06F2212/7205 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/0011 ,  G11C13/0023 ,  G11C13/0061 ,  G11C13/0069 ,  G11C2213/31 ,  G11C2213/32

摘要： An integrated circuit includes memory segments, each having at least one memory cell configurable in first and second states to store data, and a controller that controls programming and erasing of the memory segments. The controller maps external memory addresses of write data to internal memory addresses of erased memory segments with no memory cells in the first state such that erased memory segments are programmed with write data. When a write access occurs for an external memory address previously mapped to an internal memory address of a programmed memory segment with at least one memory cell in the first state, the controller remaps the external memory address to another internal memory address of an erased memory segment. The controller identifies programmed memory segments to be erased and controls selective erasure of the identified programmed memory segments, such as programmed memory segments no longer mapped to an external memory address.

摘要翻译： 集成电路包括存储器段，每个存储器段具有可在第一和第二状态下配置以存储数据的至少一个存储单元，以及控制存储器段的编程和擦除的控制器。 控制器将写入数据的外部存储器地址映射到已擦除存储器段的内部存储器地址，而没有存储器单元处于第一状态，使得擦除的存储器段被编写为写入数据。 当对于先前映射到具有处于第一状态的至少一个存储器单元的编程存储器段的内部存储器地址的外部存储器地址进行写访问时，控制器将外部存储器地址重新映射到擦除的存储器段的另一内部存储器地址 。 控制器识别要擦除的已编程存储器段，并且控制所识别的已编程存储器段的选择性擦除，例如不再映射到外部存储器地址的编程存储器段。

公开(公告)号：US07425861B2

公开(公告)日：2008-09-16

申请号：US11477077

申请日：2006-06-28

申请人： Jens Egerer ,  Rainer Bartenschlager ,  Helmut Schneider

发明人： Jens Egerer ,  Rainer Bartenschlager ,  Helmut Schneider

IPC分类号： G05F1/10

CPC分类号： G11C7/08 ,  G11C7/04 ,  G11C7/06

摘要： A method and a device for regulating the threshold voltage of a transistor is disclosed. The device includes a circuit configured for modifying a voltage applied at a bulk connection of the transistor such that the threshold voltage of the transistor is substantially temperature-independent at least in a first temperature range. In one embodiment, the device includes a memory device, and the transistor is a transistor of a sense amplifier of the memory device.

摘要翻译： 公开了一种用于调节晶体管的阈值电压的方法和装置。 该器件包括电路，其被配置为修改在晶体管的体连接处施加的电压，使得晶体管的阈值电压至少在第一温度范围内基本上与温度无关。 在一个实施例中，器件包括存储器件，晶体管是存储器件的读出放大器的晶体管。

公开(公告)号：US07405991B2

公开(公告)日：2008-07-29

申请号：US10812395

申请日：2004-03-30

申请人： Jens Egerer

发明人： Jens Egerer

IPC分类号： H02J3/00 ,  G11C5/14 ,  H01L23/02

CPC分类号： G11C5/063 ,  H01L23/50 ,  H01L24/48 ,  H01L24/49 ,  H01L25/0657 ,  H01L2224/48145 ,  H01L2224/49113 ,  H01L2225/06506 ,  H01L2924/00014 ,  H01L2924/12042 ,  H01L2924/1306 ,  Y10T307/461 ,  H01L2924/00 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

摘要： The invention is directed to a system and method comprising a first semiconductor device and a second semiconductor device, wherein the first semiconductor device comprises a voltage supply means, characterized in that the voltage supply means of the first semiconductor device is connected to the second semiconductor device, so that the voltage supply means of the first semiconductor device can provide a supply voltage for the second semiconductor device.

摘要翻译： 本发明涉及一种包括第一半导体器件和第二半导体器件的系统和方法，其中所述第一半导体器件包括电压供应器件，其特征在于，所述第一半导体器件的电压供应器件连接到所述第二半导体器件 使得第一半导体器件的电压提供装置可以为第二半导体器件提供电源电压。

公开(公告)号：US20070274147A1

公开(公告)日：2007-11-29

申请号：US11746173

申请日：2007-05-09

申请人： Jens Egerer

发明人： Jens Egerer

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40626 ,  G11C29/028 ,  G11C29/50 ,  G11C2029/5002 ,  G11C2211/4061

摘要： An integrated semiconductor memory that has at least one temperature measuring element and repeatedly carries out a temperature measurement during the operation of the semiconductor memory, wherein the semiconductor memory repeats the temperature measurement at instants corresponding to a measuring frequency of the temperature measuring element. According to an embodiment of the invention, the measuring frequency of the temperature measuring element is variable and the temperature measuring element is driven in such a way that the measuring frequency changes in a manner dependent on the temporal development of measured values of the repeated temperature measurements.

摘要翻译： 一种具有至少一个温度测量元件并在半导体存储器的操作期间重复进行温度测量的集成半导体存储器，其中半导体存储器在对应于温度测量元件的测量频率的时刻重复温度测量。 根据本发明的实施例，温度测量元件的测量频率是可变的，并且温度测量元件被驱动，使得测量频率以取决于重复温度测量值的测量值的时间发展的方式变化 。

公开(公告)号：US06768693B2

公开(公告)日：2004-07-27

申请号：US10368333

申请日：2003-02-18

申请人： Robert Feurle ,  Thomas Borst ,  Jens Egerer

发明人： Robert Feurle ,  Thomas Borst ,  Jens Egerer

IPC分类号： G11C700

CPC分类号： G11C7/04 ,  G11C11/406 ,  G11C2207/2227

摘要： An integrated dynamic memory contains a control circuit for controlling a refresh mode in which the memory cells undergo refreshing of their contents. A controllable frequency generator serves for setting a refresh frequency. A temperature sensor circuit detects a temperature of the memory and outputs a first reference value, and an externally writable circuit is provided for outputting a second reference value. The temperature sensor circuit and the externally writable circuit are alternatively connectible to the control input of the frequency generator for setting the refresh frequency. If the externally writable circuit has been written, the second reference value, which corresponds to a temperature, is fed to the frequency generator; otherwise, the first reference value is supplied. In this manner, users of the memory that are unable to measure temperature can expediently optimize the power consumption that is necessary for standby mode and reduce it at low temperatures.

摘要翻译： 集成动态存储器包含用于控制刷新模式的控制电路，其中存储器单元经历其内容刷新。 可控频率发生器用于设置刷新频率。 温度传感器电路检测存储器的温度并输出第一参考值，并且提供外部可写入电路以输出第二参考值。 温度传感器电路和外部可写入电路可替换地连接到频率发生器的控制输入端，用于设定刷新频率。 如果写入外部可写入电路，则将对应于温度的第二参考值馈送到频率发生器; 否则，提供第一个参考值。 以这种方式，不能测量温度的存储器的用户可以方便地优化待机模式所需的功耗并在低温下降低功耗。