公开(公告)号：US20100309742A1

公开(公告)日：2010-12-09

申请号：US12768060

申请日：2010-04-27

Applicant: Ho-Cheol LEE ,  Jung-Bae LEE

Inventor： Ho-Cheol LEE ,  Jung-Bae LEE

IPC: G11C5/14 ,  G11C8/16

CPC classification number: G11C5/148 ,  G11C5/144 ,  G11C5/147 ,  G11C8/16

Abstract: Disclosed is a method of controlling a deep power down mode in a multi-port semiconductor memory having a plurality of ports connected to a plurality of processors. Control of the deep power down mode in the multi-port semiconductor memory is performed such that activation/deactivation of the deep power down mode are determined in accordance with signals applied through various ports in the plurality of ports.

Abstract translation: 公开了一种在多端口半导体存储器中控制深度掉电模式的方法，该多端口半导体存储器具有连接到多个处理器的多个端口。 执行多端口半导体存储器中的深度掉电模式的控制，使得根据通过多个端口中的各个端口施加的信号来确定深度掉电模式的激活/去激活。

公开(公告)号：US20080195922A1

公开(公告)日：2008-08-14

申请号：US11779345

申请日：2007-07-18

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G06F11/10

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

公开(公告)号：US20080195914A1

公开(公告)日：2008-08-14

申请号：US11862409

申请日：2007-09-27

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: H03M13/05

CPC classification number: G06F11/1008

Abstract: A memory system including a memory controller and a memory and a related method are disclosed. The method includes communicating a command and error detection/correction (EDC) data associated with the command from the memory controller to the memory, decoding the command and executing an EDC operation related to the EDC data in parallel, and if the command is a write command, delaying execution of a write operation indicated by the write command until completion of the EDC operation, else immediately executing an operation indicated by the command without regard to completion of the EDC operation.

Abstract translation: 公开了一种包括存储器控制器和存储器以及相关方法的存储器系统。 该方法包括将与命令相关联的命令和错误检测/校正（EDC）数据从存储器控制器传送到存储器，解码该命令并并行执行与EDC数据相关的EDC操作，并且如果命令是写入 命令，延迟执行由写入命令指示的写入操作，直到完成EDC操作，否则立即执行由命令指示的操作，而不考虑完成EDC操作。

公开(公告)号：US20080022179A1

公开(公告)日：2008-01-24

申请号：US11779977

申请日：2007-07-19

Applicant: Jung-Bae LEE

Inventor： Jung-Bae LEE

IPC: G06F11/08 ,  G08C25/02

CPC classification number: H04L1/1671 ,  H04L1/0025 ,  H04L25/0272 ,  H04L25/0278 ,  H04L25/0288 ,  H04L25/03038 ,  H04L25/03057 ,  H04L25/03885

Abstract: A system having a transmission unit transmitting an output data signal formed from output data and related error detection code and a corresponding receiving unit. The output data signal is pre-emphasized by a pre-emphasis driver in the transmission unit. The receiving unit includes an equalizer equalizing the received output data signal and an error detector analyzing the error detection code to determine whether a bit error is present in the received data. Upon successive data transmission failures either an equalization coefficient in the equalizer or a pre-emphasis coefficient in the pre-emphasis driver are changed.

Abstract translation: 一种具有发送单元的系统，该发送单元发送由输出数据和相关错误检测码形成的输出数据信号和相应的接收单元。 输出数据信号由传输单元中的预加重驱动器预先强调。 接收单元包括均衡接收的输出数据信号的均衡器和分析错误检测码的误差检测器，以确定接收数据中是否存在位错误。 在连续数据传输故障时，均衡器中的均衡系数或预加重驱动器中的预加重系数被改变。

公开(公告)号：US20080013357A1

公开(公告)日：2008-01-17

申请号：US11863151

申请日：2007-09-27

Applicant: Chul-Woo PARK ,  Sung-Hoon KIM ,  Hyuk-Joon KWON ,  Jung-Bae LEE ,  Youn-Sik PARK

Inventor： Chul-Woo PARK ,  Sung-Hoon KIM ,  Hyuk-Joon KWON ,  Jung-Bae LEE ,  Youn-Sik PARK

IPC: G11C5/06

CPC classification number: H01L27/0207 ,  G11C5/025 ,  G11C5/063 ,  G11C7/18 ,  H01L23/5226 ,  H01L27/0203 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/10897 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor memory device and an arrangement method thereof are disclosed. The semiconductor memory device comprises column selecting signal lines and global data IO signal lines arranged on the same layer in the same direction above a memory cell array; word lines and first local data IO signal lines arranged on a different layer from the column selecting signal lines above the memory cell array, in a perpendicular direction to the column selecting signal lines; and second local data IO signal lines arranged on a different layer from the column selecting signal lines and the word lines above the memory cell array, in the same direction as the first local data IO signal lines.

Abstract translation: 公开了一种半导体存储器件及其布置方法。 半导体存储器件包括在存储单元阵列上方沿相同方向布置在同一层上的列选择信号线和全局数据IO信号线; 在与列选择信号线垂直的方向上与位于存储单元阵列上方的列选择信号线布置在不同层上的字线和第一本地数据IO信号线; 以及在与第一本地数据IO信号线相同的方向上与列选择信号线和存储单元阵列上方的字线​​布置在不同层上的第二本地数据IO信号线。

公开(公告)号：US20070250658A1

公开(公告)日：2007-10-25

申请号：US11745965

申请日：2007-05-08

Applicant: Jung-Bae LEE ,  Hoe-Ju CHUNG

Inventor： Jung-Bae LEE ,  Hoe-Ju CHUNG

IPC: G11C5/06

CPC classification number: G06F13/1673 ,  G06F13/1684

Abstract: The invention provides an improved memory system that addresses signal degradation due to transmission line effects. The improved memory system includes a first buffer, at least one first memory device coupled to the first buffer, and a plurality of signal traces. The first buffer and memory device are mounted on a motherboard. Likewise, the plurality of signal traces is routed on the motherboard. Doing so eliminates stub loads that cause signal reflection that, in turn, result in signal degradation.

Abstract translation: 本发明提供了一种改进的存储器系统，其解决了由于传输线效应引起的信号劣化。 改进的存储器系统包括第一缓冲器，耦合到第一缓冲器的至少一个第一存储器件和多个信号迹线。 第一个缓冲器和存储器件安装在主板上。 同样地，多个信号迹线在主板上路由。 这样做可以消除引起信号反射的短线负载，从而导致信号衰减。