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公开(公告)号：US11271571B2
公开(公告)日：2022-03-08
申请号：US16909520
申请日：2020-06-23
申请人： Kandou Labs SA
发明人： Armin Tajalli , Ali Hormati
摘要： Multi-mode non-return-to-zero (NRZ) and orthogonal differential vector signaling (ODVS) clock and data recovery circuits having configurable sub-channel multi-input comparator (MIC) circuits for forming a composite phase-error signal from a plurality of data-driven phase-error signals generated using phase detectors in a plurality of receivers configured as ODVS sub-channel MICs generating orthogonal sub-channel outputs in a first mode and a separate first and second data driven phase-error signal from two receivers of a plurality of receivers configured as NRZ receivers in a second mode.
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公开(公告)号：US11265140B2
公开(公告)日：2022-03-01
申请号：US16813526
申请日：2020-03-09
申请人： Kandou Labs SA
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving N phases of a local clock signal and M phases of a reference signal, wherein M is an integer greater than or equal to 1 and N is an integer greater than or equal to 2, generating a plurality of partial phase error signals, each partial phase error signal formed at least in part by comparing (i) a respective phase of the M phases of the reference signal to (ii) a respective phase of the N phases of the local clock signal, and generating a composite phase error signal by summing the plurality of partial phase error signals, and responsively adjusting a fixed phase of a local oscillator using the composite phase error signal.
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公开(公告)号：US11245402B2
公开(公告)日：2022-02-08
申请号：US17327512
申请日：2021-05-21
申请人： Kandou Labs SA
发明人： Armin Tajalli
IPC分类号： H03L7/08 , H03L7/087 , H03L7/099 , H04L7/033 , H04L25/14 , H04L25/02 , H04L25/40 , H04L25/493 , H03K19/21 , H03L7/089 , H04L7/00
摘要： Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
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14.发明申请公开(公告)号：US20210305993A1
公开(公告)日：2021-09-30
申请号：US17347589
申请日：2021-06-15
申请人： Kandou Labs SA
摘要： Methods and systems are described for generating a process-voltage-temperature (PVT)-dependent reference voltage at a reference branch circuit based on a reference current obtained via a band gap generator and a common mode voltage input, generating a PVT-dependent output voltage at an output of a static analog calibration circuit responsive to the common mode voltage input and an adjustable current, adjusting the adjustable current through the static analog calibration circuit according to a control signal generated responsive to comparisons of the PVT-dependent output voltage to the PVT-dependent reference voltage, and configuring a clocked data sampler with a PVT-calibrated current by providing the control signal to the clocked data sampler.
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公开(公告)号：US10958251B2
公开(公告)日：2021-03-23
申请号：US16843785
申请日：2020-04-08
申请人： Kandou Labs SA
摘要： Methods and systems are described for generating multiple phases of a local clock at a controllable variable frequency, using loop-connected strings of active circuit elements. A specific embodiment incorporates a loop of four active circuit elements, each element providing true and complement outputs that are cross-coupled to maintain a fixed phase relationship, and feed-forward connections at each loop node to facilitate high frequency operation. A particular physical layout is described that maximizes operating frequency and minimizes clock pertubations caused by unbalanced or asymmetric signal paths and parasitic node capacitances.
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公开(公告)号：US20200313841A1
公开(公告)日：2020-10-01
申请号：US16903001
申请日：2020-06-16
申请人： Kandou Labs SA
发明人： Roger Ulrich , Armin Tajalli , Ali Hormati , Richard Simpson
摘要： Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.
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17.发明申请公开(公告)号：US20200177363A1
公开(公告)日：2020-06-04
申请号：US16781910
申请日：2020-02-04
申请人： Kandou Labs SA
发明人： Armin Tajalli
摘要： Methods and systems are described for receiving a reference clock signal and a phase of a local oscillator signal at a dynamically-weighted XOR gate comprising a plurality of logic branches, generating a plurality of weighted segments of a phase-error signal, the plurality of weighted segments including positive weighted segments and negative weighted segments, each weighted segment of the phase-error signal having a respective weight applied by a corresponding logic branch of the plurality of logic branches, generating an aggregate control signal based on an aggregation of the weighted segments of the phase-error signal, and outputting the aggregate control signal as a current-mode output for controlling a local oscillator generating the phase of the local oscillator signal, the local oscillator configured to induce a phase offset into the local oscillator signal in response to the aggregate control signal.
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公开(公告)号：US11251934B2
公开(公告)日：2022-02-15
申请号：US16903001
申请日：2020-06-16
申请人： Kandou Labs SA
发明人： Roger Ulrich , Armin Tajalli , Ali Hormati , Richard Simpson
摘要： Generating, during a first and second signaling interval, an aggregated data signal by forming a linear combination of wire signals received in parallel from wires of a multi-wire bus, wherein at least some of the wire signals undergo a signal level transition during the first and second signaling interval; measuring a signal skew characteristic of the aggregated data signal; and, generating wire-specific skew offset metrics, each wire-specific skew offset metric based on the signal skew characteristic.
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公开(公告)号：US20210336824A1
公开(公告)日：2021-10-28
申请号：US17367392
申请日：2021-07-04
申请人： Kandou Labs SA
发明人： Armin Tajalli
IPC分类号： H04L27/20 , H04L25/02 , H04L25/49 , H04L27/148 , H04L27/26
摘要： Methods and systems are described for obtaining a set of carrier-modulated symbols of a carrier-modulated codeword, each carrier-modulated symbol received via a respective wire of a plurality of wires of a multi-wire bus, applying each carrier-modulated symbol of the set of carrier-modulated symbols to a corresponding transistor of a set of transistors, the set of transistors further connected to a pair of output nodes according to a sub-channel vector of a plurality of mutually orthogonal sub-channel vectors, recovering a demodulation signal from the carrier-modulated symbols, and generating a demodulated sub-channel data output as a differential voltage on the pair of output nodes based on a linear combination of the set of carrier-modulated symbols by controlling conductivity of the set of transistors according to the demodulation signal.
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公开(公告)号：US20210320662A1
公开(公告)日：2021-10-14
申请号：US17327512
申请日：2021-05-21
申请人： Kandou Labs SA
发明人： Armin Tajalli
IPC分类号： H03L7/08 , H03L7/087 , H03L7/099 , H04L7/033 , H04L25/14 , H04L25/02 , H04L25/40 , H04L25/493 , H03K19/21 , H03L7/089
摘要： Generating a composite interpolated phase-error signal for clock phase adjustment of a local oscillator by forming a summation of weighted phase-error signals generated using a matrix of partial phase comparators, each of which compare a phase of the local oscillator with a corresponding phase of a reference clock.
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