公开(公告)号：US20240031588A1

公开(公告)日：2024-01-25

申请号：US18479521

申请日：2023-10-02

Applicant: KIOXIA CORPORATION

Inventor： Daisuke YASHIMA ,  Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Takashi MIURA ,  Kohei OIKAWA ,  Sho KODAMA ,  Youhei FUKAZAWA ,  Zheye WANG

IPC: H04N19/423 ,  H04N19/146 ,  H04N19/13

CPC classification number: H04N19/423 ,  H04N19/146 ,  H04N19/13 ,  H04N19/184

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

公开(公告)号：US20230006689A1

公开(公告)日：2023-01-05

申请号：US17688368

申请日：2022-03-07

Applicant: Kioxia Corporation

Inventor： Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Kohei OIKAWA ,  Sho KODAMA

IPC: H03M7/30 ,  G06F3/06

Abstract: According to one embodiment, an interleaving unit divides a symbol string into first and second symbols. A first coding unit converts the first symbols to first codewords. A first packet generating unit generates first packets including the first codewords. A first request generating unit generates first packet requests including sizes of variable length packets. A second coding unit converts the second symbols to second codewords. A second packet generating unit generates second packets including the second codewords. A second request generating unit generates second packet requests including sizes of variable length packets. A multiplexer outputs a compressed stream including the first and second variable length packets cut out from the first and second packets.

公开(公告)号：US20210250043A1

公开(公告)日：2021-08-12

申请号：US17015874

申请日：2020-09-09

Applicant: Kioxia Corporation

Inventor： Kohei OIKAWA ,  Masato SUMIYOSHI

IPC: H03M7/42 ,  G06F3/06

Abstract: According to one embodiment, a dividing circuit divides a first bit string into second bit strings and outputs the divided second bit strings. The dividing circuit includes first, second, and third blocks. The first block executes first operation for each bit of a third bit string in the first bit string. The first operation is to calculate a head bit of a succeeding symbol when one bit is assumed to be a head of one symbol. The second block executes second operation for each bit of the third bit string for a set number of times. The second operation is to overwrite boundary information associated with one bit with boundary information associated with a bit indicated by the boundary information. The third block divides the third bit string immediately before a second bit indicated by boundary information associated with a first bit of the third bit string.

公开(公告)号：US20210064524A1

公开(公告)日：2021-03-04

申请号：US16806173

申请日：2020-03-02

Applicant: KIOXIA CORPORATION

Inventor： Keiri NAKANISHI ,  Konosuke WATANABE ,  Kohei OIKAWA ,  Daisuke IWAI

IPC: G06F12/02 ,  G06F13/16 ,  G11C16/34 ,  G11C16/10

Abstract: A memory system includes a first memory that is nonvolatile, a second memory that is volatile, and a memory controller. The memory controller is configured to store first information in the second memory. The first information includes management information. The memory controller is further configured to compress the first information. The compressed first information is second information. The memory controller is configured to store the second information in the first memory.

公开(公告)号：US20240303188A1

公开(公告)日：2024-09-12

申请号：US18593215

申请日：2024-03-01

Applicant: Kioxia Corporation

Inventor： Takashi TAKEMOTO ,  Kensaku YAMAGUCHI ,  Keiri NAKANISHI ,  Kohei OIKAWA ,  Sho KODAMA

IPC: G06F12/02

CPC classification number: G06F12/0246 ,  G06F12/0253 ,  G06F2212/7201

Abstract: A memory system includes a nonvolatile memory and a controller. The controller is configured to maintain an address mapping table including first mapping information indicating correspondence between logical addresses and physical addresses of the nonvolatile memory in units of physical regions each having a predetermined size. The controller, during a write operation compresses write data of the predetermined size into a compressed write data, determines a physical address range in which the compressed write data is to be written, writes the compressed write data into the physical address range and also second mapping information into an area in one or more physical regions spanned by the physical address range, and updates the address mapping table. The second mapping information indicates a logical address of the write data, an information capable of specifying an offset, and a size of the compressed write data.

公开(公告)号：US20240004549A1

公开(公告)日：2024-01-04

申请号：US18178472

申请日：2023-03-03

Applicant: Kioxia Corporation

Inventor： Kohei OIKAWA

IPC: G06F3/06

CPC classification number: G06F3/0608 ,  G06F3/0679 ,  G06F3/0656

Abstract: A memory system includes a non-volatile memory, a buffer memory, and a controller configured to write data to the non-volatile memory in write units of a predefined size, each write unit including a plurality of data items and log data and to temporarily store the data items and the log data of each write unit in the buffer memory prior to writing the write unit to the non-volatile memory. In response to a write command, the controller calculates a total data size of the data items of the write unit and write data specified in the write command, and a total log size of the log data and log information associated with the write data, and in response to determining that the total data size or the total log size is greater than their respective thresholds, write the write unit stored in the buffer memory to the non-volatile memory.

公开(公告)号：US20230070623A1

公开(公告)日：2023-03-09

申请号：US17653513

申请日：2022-03-04

Applicant: Kioxia Corporation

Inventor： Daisuke YASHIMA ,  Youhei FUKAZAWA ,  Sho KODAMA ,  Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Kohei OIKAWA ,  Zheye WANG ,  Takashi MIURA

IPC: H03M7/30

Abstract: According to one embodiment, a data compression device includes a dictionary match determination unit, an extended matching generator, a match selector and a match connector. The dictionary match determination unit searches for first past input data matching first new input data. The extended matching generator compares second past input data subsequent to the first past input data with second new input data subsequent to the first new input data. The match selector generates compressed data by replacing a part of the input data with match information output from the dictionary match determination unit or the extended matching generator. The match connector replaces a plurality of match information in the compressed data with single match information.

公开(公告)号：US20220398019A1

公开(公告)日：2022-12-15

申请号：US17686246

申请日：2022-03-03

Applicant: KIOXIA CORPORATION

Inventor： Youhei FUKAZAWA ,  Sho KODAMA ,  Keiri NAKANISHI ,  Kohei OIKAWA ,  Takashi MIURA ,  Daisuke YASHIMA ,  Masato SUMIYOSHI ,  Zheye WANG

IPC: G06F3/06

Abstract: A compression device includes an analyzer circuit, a control circuit, a compressor circuit, and a selector circuit. The analyzer circuit is configured to analyze first data that is input thereto and generate one or more parameter values regarding data compression and/or decompression. The control circuit is configured to generate at least one compression mode information indicating whether or not compression is to be performed, based on the one or more parameter values. The compressor circuit is configured to compress the first data into second data according to the compression mode information. The selector circuit is configured to output the first data if not compressed or the second data if the first data is compressed, together with the compression mode information.

公开(公告)号：US20220353519A1

公开(公告)日：2022-11-03

申请号：US17868597

申请日：2022-07-19

Applicant: Kioxia Corporation

Inventor： Daisuke YASHIMA ,  Masato SUMIYOSHI ,  Keiri NAKANISHI ,  Takashi MIURA ,  Kohei OIKAWA ,  Sho KODAMA ,  Youhei FUKAZAWA ,  Zheye WANG

IPC: H04N19/423 ,  H04N19/146 ,  H04N19/13

Abstract: According to one embodiment, a memory system includes a frequency value update unit, a first intra-group rearranging unit, a second intra-group rearranging unit, and a routing unit. The frequency value update unit adds a first value to each of one or more first frequency values that are associated with one or more first symbols, respectively, in one or more entries in a table. The first intra-group rearranging unit rearranges first entries, which belong to a first group, using frequency values in the first entries. The second intra-group rearranging unit rearranges second entries, which belong to a second group lower than the first group, using frequency values. The routing unit rearranges at least one of the first entries and at least one of the second entries.

公开(公告)号：US20220269416A1

公开(公告)日：2022-08-25

申请号：US17304025

申请日：2021-06-14

Applicant: Kioxia Corporation

Inventor： Sho KODAMA ,  Keiri NAKANISHI ,  Masato SUMIYOSHI ,  Zheye WANG ,  Kohei OIKAWA ,  Youhei FUKAZAWA ,  Daisuke YASHIMA ,  Takashi MIURA

IPC: G06F3/06 ,  H03M7/30

Abstract: According to one embodiment, a memory system includes a compressor configured to output second data obtained by compressing input first data and a non-volatile memory to which third data based on the second data output from the compressor is written. The compressor includes a dictionary coding unit configured to perform dictionary coding on the first data, an entropy coding unit configured to perform entropy coding on the result of the dictionary coding, a first calculation unit configured to calculate compression efficiencies of the dictionary coding and the entropy coding, and a first control unit configured to control an operation of at least one of the dictionary coding unit and the entropy coding unit based on the compression efficiencies and a power reduction level.