公开(公告)号：US07457181B2

公开(公告)日：2008-11-25

申请号：US11600552

申请日：2006-11-16

申请人： Hoon Lee ,  Kee-Won Kwon

发明人： Hoon Lee ,  Kee-Won Kwon

IPC分类号： G11C7/02

CPC分类号： G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065

摘要： A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The detecting unit detects a potential difference between the global input/output line pair. The detect control signal generating unit disables an operation of the sense amplifier and precharges the global input/output line pair to a predetermined voltage. A precharge operation of a memory device may be performed at a higher speed so that a high speed operation of the memory device may be achieved. In addition, the operating time of the sense amplifier may be decreased so that the power consumption of the memory device may be reduced.

摘要翻译： 存储器件具有配置用于数据传输的全局输入/输出线对。 存储装置包括读出放大器，检测单元和检测控制信号生成单元。 读出放大器耦合到全局输入/输出线对。 检测单元检测全局输入/输出线对之间的电位差。 检测控制信号产生单元禁止读出放大器的操作，并将全局输入/输出线对预充电到预定电压。 可以以更高的速度执行存储器件的预充电操作，从而可以实现存储器件的高速操作。 此外，可以减小读出放大器的工作时间，从而可以降低存储器件的功耗。

公开(公告)号：US07199632B2

公开(公告)日：2007-04-03

申请号：US11147629

申请日：2005-06-08

申请人： Byung-Kwan Chun ,  Kee-Won Kwon

发明人： Byung-Kwan Chun ,  Kee-Won Kwon

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.

摘要翻译： 提供了一种用于与外部时钟同步并且校正占空比的半导体器件中的占空比校正电路。 占空比校正电路包括具有至少一个或多个晶体管的反相器结构的调制器。 调制器通过源极端子和任何一个晶体管的大部分接收控制信号，并根据外部时钟信号校正占空比。 占空比校正电路还包括将调制器的输出信号转换成全摆幅电平并输出调制器的转换的输出信号的驱动器，以及响应于驱动器的输出信号产生控制信号的反馈回路 。

公开(公告)号：US07145493B2

公开(公告)日：2006-12-05

申请号：US11141536

申请日：2005-05-31

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： H03M1/66

CPC分类号： H03M1/1061 ,  H03M1/785

摘要： A DAC circuit can include a plurality of current source circuits configured to operate responsive to respective different bias voltage signals and respective true and complementary binary digit signals.

摘要翻译： DAC电路可以包括多个电流源电路，其被配置为响应于各个不同的偏置电压信号和相应的真和互补的二进制数字信号进行操作。

公开(公告)号：US09330743B2

公开(公告)日：2016-05-03

申请号：US14677991

申请日：2015-04-03

申请人： Chan-Kyung Kim ,  Kee-Won Kwon ,  Su-A Kim ,  Chul-Woo Park ,  Jae-Youn Youn

发明人： Chan-Kyung Kim ,  Kee-Won Kwon ,  Su-A Kim ,  Chul-Woo Park ,  Jae-Youn Youn

IPC分类号： G11C11/00 ,  G11C11/16 ,  G11C5/08 ,  G11C7/06 ,  G11C5/02 ,  G11C13/00 ,  G11C11/4091

CPC分类号： G11C11/16 ,  G11C5/025 ,  G11C5/08 ,  G11C7/065 ,  G11C11/161 ,  G11C11/1653 ,  G11C11/1655 ,  G11C11/1659 ,  G11C11/1673 ,  G11C11/4091 ,  G11C13/0023 ,  G11C13/004 ,  G11C2013/0042 ,  G11C2213/79 ,  G11C2213/82

摘要： A memory core of a resistive type memory device includes at least a first resistive type memory cell coupled to a bit-line, a first resistance to voltage converter and a bit-line sense amplifier. The first resistance to voltage converter is coupled to the bit-line at a first node. The first resistance to voltage converter converts a resistance of the first resistive type memory cell to a corresponding voltage based on a read column selection signal. The bit-line sense amplifier is coupled to the bit-line at the first node and is coupled to a complementary bit-line at a second node. The bit-line sense amplifier senses and amplifies a voltage difference of the bit-line and the complementary bit-line in response to a sensing control signal.

摘要翻译： 电阻型存储器件的存储核心至少包括耦合到位线的第一电阻型存储单元，第一电阻转换器和位线读出放大器。 第一电阻转换器在第一节点处耦合到位线。 第一电阻转换器基于读列选择信号将第一电阻型存储单元的电阻转换成相应的电压。 位线读出放大器耦合到第一节点处的位线，并且耦合到第二节点处的互补位线。 位线检测放大器响应于感测控制信号而感测和放大位线和互补位线的电压差。

公开(公告)号：US20070286259A1

公开(公告)日：2007-12-13

申请号：US11790174

申请日：2007-04-24

申请人： Duk-Min Kwon ,  Kee-Won Kwon

发明人： Duk-Min Kwon ,  Kee-Won Kwon

IPC分类号： G01K7/00

CPC分类号： G01K7/015 ,  G01K15/00 ,  G01K2219/00

摘要： A self-calibrating temperature sensor and a method thereof are provided. The self-calibrating temperature sensor may include a reference voltage generator to generate a reference voltage based on temperature, a digital-to-analog converter to convert a first digital signal into an analog sensing voltage, a comparator to compare the reference voltage with the analog sensing voltage, and to generate a comparison result signal, a digital signal generator to generate and update the first digital signal based on the comparison result signal, a first storage circuit to store the first digital signal based on a first temperature, a data output unit to output data corresponding to a second temperature based on the first digital signal and a second digital signal output from the first storage circuit.

摘要翻译： 提供了一种自校准温度传感器及其方法。 自校准温度传感器可以包括参考电压发生器以产生基于温度的参考电压，数模转换器将第一数字信号转换为模拟感测电压，比较器将参考电压与模拟 并且产生比较结果信号，数字信号发生器，用于基于比较结果信号产生和更新第一数字信号;第一存储电路，用于基于第一温度存储第一数字信号;数据输出单元 基于第一数字信号输出对应于第二温度的数据和从第一存储电路输出的第二数字信号。

公开(公告)号：US20070109892A1

公开(公告)日：2007-05-17

申请号：US11600552

申请日：2006-11-16

申请人： Hoon Lee ,  Kee-Won Kwon

发明人： Hoon Lee ,  Kee-Won Kwon

IPC分类号： G11C7/02

CPC分类号： G11C11/4096 ,  G11C7/065 ,  G11C7/1048 ,  G11C7/1051 ,  G11C7/106 ,  G11C11/4091 ,  G11C2207/002 ,  G11C2207/065

摘要： A memory device has a global input/output line pair configured for data transfer. The memory device includes a sense amplifier, a detecting unit and a detect control signal generating unit. The sense amplifier is coupled to the global input/output line pair. The detecting unit detects a potential difference between the global input/output line pair. The detect control signal generating unit disables an operation of the sense amplifier and precharges the global input/output line pair to a predetermined voltage. A precharge operation of a memory device may be performed at a higher speed so that a high speed operation of the memory device may be achieved. In addition, the operating time of the sense amplifier may be decreased so that the power consumption of the memory device may be reduced.

摘要翻译： 存储器件具有配置用于数据传输的全局输入/输出线对。 存储装置包括读出放大器，检测单元和检测控制信号生成单元。 读出放大器耦合到全局输入/输出线对。 检测单元检测全局输入/输出线对之间的电位差。 检测控制信号产生单元禁止读出放大器的操作，并将全局输入/输出线对预充电到预定电压。 可以以更高的速度执行存储器件的预充电操作，从而可以实现存储器件的高速操作。 此外，可以减小读出放大器的工作时间，从而可以降低存储器件的功耗。

公开(公告)号：US07199623B2

公开(公告)日：2007-04-03

申请号：US10968018

申请日：2004-10-20

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： H03L7/00

CPC分类号： H03K17/223

摘要： A power-on reset circuit and method for the same may provide reset signals during power-up and/or power-down cycles, to reduce the chances of error. An error may occur, for example, due to voltage fluctuations and/or the ambient temperature of circuit components. Reducing the chances of error during a power-up cycle may include setting an output node of a circuit to a reset state when a power supply voltage reaches a first voltage level and outputting a power-on reset signal to the output node when the power supply voltage equals a second voltage level higher than the first. Reducing the chances of error during a power-down cycle may include setting the output node to a reset state when the output node reaches a third voltage level between the first and second voltage levels.

摘要翻译： 上电复位电路及其方法可以在上电和/或掉电周期期间提供复位信号，以减少错误的可能性。 例如，由于电压波动和/或电路部件的环境温度可能会发生错误。 在上电周期中减少错误的可能性可以包括当电源电压达到第一电压电平时将电路的输出节点设置为复位状态，并且当电源供应时将输出电源复位信号输出到输出节点 电压等于高于第一电压的第二电压电平。 在掉电周期中降低错误的可能性可以包括当输出节点达到第一和第二电压电平之间的第三电压电平时将输出节点设置为复位状态。

公开(公告)号：US20050285649A1

公开(公告)日：2005-12-29

申请号：US11147629

申请日：2005-06-08

申请人： Byung-Kwan Chun ,  Kee-Won Kwon

发明人： Byung-Kwan Chun ,  Kee-Won Kwon

IPC分类号： G11C7/22 ,  H02M1/12 ,  H03K5/156

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.

摘要翻译： 提供了一种用于与外部时钟同步并且校正占空比的半导体器件中的占空比校正电路。 占空比校正电路包括具有至少一个或多个晶体管的反相器结构的调制器。 调制器通过源极端子和任何一个晶体管的大部分接收控制信号，并根据外部时钟信号校正占空比。 占空比校正电路还包括将调制器的输出信号转换成全摆幅电平并输出调制器的转换的输出信号的驱动器，以及响应于驱动器的输出信号产生控制信号的反馈回路 。

公开(公告)号：US20050270077A1

公开(公告)日：2005-12-08

申请号：US10968018

申请日：2004-10-20

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： H03K17/22 ,  H03L7/00

CPC分类号： H03K17/223

摘要： A power-on reset circuit and method for the same may provide reset signals during power-up and/or power-down cycles, to reduce the chances of error. An error may occur, for example, due to voltage fluctuations and/or the ambient temperature of circuit components. Reducing the chances of error during a power-up cycle may include setting an output node of a circuit to a reset state when a power supply voltage reaches a first voltage level and outputting a power-on reset signal to the output node when the power supply voltage equals a second voltage level higher than the first. Reducing the chances of error during a power-down cycle may include setting the output node to a reset state when the output node reaches a third voltage level between the first and second voltage levels.

摘要翻译： 上电复位电路及其方法可以在上电和/或掉电周期期间提供复位信号，以减少错误的可能性。 例如，由于电压波动和/或电路部件的环境温度可能会发生错误。 在上电周期中减少错误的可能性可以包括当电源电压达到第一电压电平时将电路的输出节点设置为复位状态，并且当电源供应时将输出电源复位信号输出到输出节点 电压等于高于第一电压的第二电压电平。 在掉电周期中降低错误的可能性可以包括当输出节点达到第一和第二电压电平之间的第三电压电平时将输出节点设置为复位状态。

公开(公告)号：US06914461B2

公开(公告)日：2005-07-05

申请号：US10402641

申请日：2003-03-28

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： G06F1/24 ,  H03K17/22 ,  H03K17/30

CPC分类号： H03K17/223

摘要： A power-on reset circuit which outputs a power-on reset signal through an output node includes a first signal generator that generates a first signal voltage. The first signal voltage increases from a ground voltage when a power supply voltage reaches a first threshold voltage. A second signal generator generates a second signal voltage, and the second signal voltage decreases from the power supply voltage when the power supply voltage reaches a second threshold voltage. A comparator activates the power-on reset signal responsive to a comparison of the first and second signals.

摘要翻译： 通过输出节点输出上电复位信号的上电复位电路包括产生第一信号电压的第一信号发生器。 当电源电压达到第一阈值电压时，第一信号电压从接地电压增加。 第二信号发生器产生第二信号电压，并且当电源电压达到第二阈值电压时，第二信号电压从电源电压降低。 响应于第一和第二信号的比较，比较器激活上电复位信号。