公开(公告)号：US07199632B2

公开(公告)日：2007-04-03

申请号：US11147629

申请日：2005-06-08

申请人： Byung-Kwan Chun ,  Kee-Won Kwon

发明人： Byung-Kwan Chun ,  Kee-Won Kwon

IPC分类号： H03K3/017

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.

摘要翻译： 提供了一种用于与外部时钟同步并且校正占空比的半导体器件中的占空比校正电路。 占空比校正电路包括具有至少一个或多个晶体管的反相器结构的调制器。 调制器通过源极端子和任何一个晶体管的大部分接收控制信号，并根据外部时钟信号校正占空比。 占空比校正电路还包括将调制器的输出信号转换成全摆幅电平并输出调制器的转换的输出信号的驱动器，以及响应于驱动器的输出信号产生控制信号的反馈回路 。

公开(公告)号：US20050285649A1

公开(公告)日：2005-12-29

申请号：US11147629

申请日：2005-06-08

申请人： Byung-Kwan Chun ,  Kee-Won Kwon

发明人： Byung-Kwan Chun ,  Kee-Won Kwon

IPC分类号： G11C7/22 ,  H02M1/12 ,  H03K5/156

CPC分类号： H03K5/1565

摘要： A duty cycle correction circuit for use in a semiconductor device, which synchronizes with an external clock and corrects a duty cycle, is provided. The duty cycle correction circuit includes a modulator of an inverter structure having at least one or more transistors. The modulator receives a control signal through a source terminal and a bulk of any one of the transistors and corrects a duty cycle in response to an external clock signal. The duty cycle correction circuit also includes a driver that converts an output signal of the modulator into a full swing level and outputs the converted output signal of the modulator, and a feedback loop that generates the control signal in response to an output signal of the driver.

摘要翻译： 提供了一种用于与外部时钟同步并且校正占空比的半导体器件中的占空比校正电路。 占空比校正电路包括具有至少一个或多个晶体管的反相器结构的调制器。 调制器通过源极端子和任何一个晶体管的大部分接收控制信号，并根据外部时钟信号校正占空比。 占空比校正电路还包括将调制器的输出信号转换成全摆幅电平并输出调制器的转换的输出信号的驱动器，以及响应于驱动器的输出信号产生控制信号的反馈回路 。

公开(公告)号：US08319425B2

公开(公告)日：2012-11-27

申请号：US12656441

申请日：2010-01-29

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： H01L51/50 ,  H01L51/52 ,  H01L51/54

CPC分类号： H01L27/3276 ,  G06K19/07749 ,  H01L27/3225 ,  H01L51/524 ,  H01Q1/2208 ,  H01Q1/36

摘要： An organic light emitting display device having RFID includes a substrate including a pixel region having at least one organic light emitting device and a non-pixel region formed on the outer circumference of the pixel region, a sealing substrate that seals at least the pixel region of the substrate, an RFID antenna pattern on the sealing substrate, and an RFID chip electrically coupled to the RFID antenna pattern.

摘要翻译： 具有RFID的有机发光显示装置包括具有至少一个有机发光元件的像素区域和形成在像素区域的外周上的非像素区域的基板，至少将像素区域 衬底，密封衬底上的RFID天线图案和电耦合到RFID天线图案的RFID芯片。

公开(公告)号：US20100207506A1

公开(公告)日：2010-08-19

申请号：US12656441

申请日：2010-01-29

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： H01J1/00

CPC分类号： H01L27/3276 ,  G06K19/07749 ,  H01L27/3225 ,  H01L51/524 ,  H01Q1/2208 ,  H01Q1/36

摘要： An organic light emitting display device having RFID includes a substrate including a pixel region having at least one organic light emitting device and a non-pixel region formed on the outer circumference of the pixel region, a sealing substrate that seals at least the pixel region of the substrate, an RFID antenna pattern on the sealing substrate, and an RFID chip electrically coupled to the RFID antenna pattern.

摘要翻译： 具有RFID的有机发光显示装置包括具有至少一个有机发光元件的像素区域和形成在像素区域的外周上的非像素区域的基板，至少将像素区域 衬底，密封衬底上的RFID天线图案和电耦合到RFID天线图案的RFID芯片。

公开(公告)号：US20060291313A1

公开(公告)日：2006-12-28

申请号：US11375808

申请日：2006-03-14

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： G11C7/02

CPC分类号： G11C7/062 ,  G11C11/4097

摘要： A sense amplifier including a pair of differential transistors configured to amplify a differential signal applied to a pair of I/O lines, each transistor having a terminal, a current supplying circuit configured to supply a current to the differential transistors in response to an enable signal, and a coupling element configured to electrically connect or disconnect the terminals of the differential transistors in response to the enable signal.

摘要翻译： 一种感测放大器，包括一对差动晶体管，其被配置为放大施加到一对I / O线的差分信号，每个晶体管具有端子;电流供应电路，被配置为响应于使能信号向差分晶体管提供电流 以及耦合元件，其被配置为响应于使能信号电连接或断开差分晶体管的端子。

公开(公告)号：US20060098519A1

公开(公告)日：2006-05-11

申请号：US11258766

申请日：2005-10-26

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： G11C8/00

CPC分类号： G11C7/1075

摘要： A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data received through a data bus to the first port in response to a leading edge of a clock signal and assigns second data received through the data bus to the second port in response to a trailing edge of the clock. Methods of operating memory devices having a dual port mode are also disclosed.

摘要翻译： 具有双端口功能的存储器件包括存储单元阵列和切换单元。 存储单元阵列具有第一端口和第二端口。 切换单元响应于时钟信号的前沿将通过数据总线接收的第一数据分配给第一端口，并且响应于时钟的后沿将通过数据总线接收的第二数据分配给第二端口。 还公开了具有双端口模式的存储器件的操作方法。

公开(公告)号：US20050270208A1

公开(公告)日：2005-12-08

申请号：US11141536

申请日：2005-05-31

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： H03M1/66 ,  H03M1/10 ,  H03M1/78

CPC分类号： H03M1/1061 ,  H03M1/785

摘要： A DAC circuit can include a plurality of current source circuits configured to operate responsive to respective different bias voltage signals and respective true and complementary binary digit signals.

摘要翻译： DAC电路可以包括多个电流源电路，其被配置为响应于各个不同的偏置电压信号和相应的真和互补的二进制数字信号而进行操作。

公开(公告)号：US07286415B2

公开(公告)日：2007-10-23

申请号：US11258766

申请日：2005-10-26

申请人： Kee-Won Kwon

发明人： Kee-Won Kwon

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C7/1075

摘要： A memory device having a dual port function includes a memory cell array and a switching unit. The memory cell array has a first port and a second port. The switching unit assigns first data received through a data bus to the first port in response to a leading edge of a clock signal and assigns second data received through the data bus to the second port in response to a trailing edge of the clock. Methods of operating memory devices having a dual port mode are also disclosed.

摘要翻译： 具有双端口功能的存储器件包括存储单元阵列和切换单元。 存储单元阵列具有第一端口和第二端口。 切换单元响应于时钟信号的前沿将通过数据总线接收的第一数据分配给第一端口，并且响应于时钟的后沿将通过数据总线接收的第二数据分配给第二端口。 还公开了具有双端口模式的存储器件的操作方法。

公开(公告)号：US06879527B2

公开(公告)日：2005-04-12

申请号：US10614013

申请日：2003-07-08

申请人： Kee-Won Kwon ,  Youn-Cheol Kim

发明人： Kee-Won Kwon ,  Youn-Cheol Kim

IPC分类号： G11C8/18 ,  G11C7/10 ,  G11C7/00

CPC分类号： G11C7/1012 ,  G11C7/1051

摘要： A semiconductor memory device includes a plurality of memory array blocks including predetermined numbers of memory cells, the memory array blocks being arranged in the row direction; a RAS chain being aligned at a side of the plurality of memory array blocks in the row direction, the RAS chain for selecting and activating a particular word line; a CAS chain being aligned at the other side of the plurality of memory array blocks in the column direction, the CAS chain for amplifying N bits of data from the plurality of memory array blocks and outputting the result to an input/output (IO) line, wherein N is a natural number more than 2; and a data converter for continuously outputting the N bits of data input via the IO line from a memory array block nearest to the RAS chain to a memory array block farthest from the RAS chain.

摘要翻译： 半导体存储器件包括多个存储器阵列块，其包括预定数量的存储器单元，存储器阵列块被布置在行方向上; RAS链在行方向上的多个存储器阵列块的一侧对齐，RAS链用于选择和激活特定字线; CAS链在列方向上在多个存储器阵列块的另一侧对准，CAS链用于从多个存储器阵列块放大N位数据，并将结果输出到输入/输出（IO）线 其中N是大于2的自然数; 以及数据转换器，用于将最靠近RAS链的存储器阵列块经由IO线输入的N位数据连续地输出到距离RAS链最远的存储器阵列块。

公开(公告)号：US5834348A

公开(公告)日：1998-11-10

申请号：US738470

申请日：1996-10-30

申请人： Kee-Won Kwon ,  Chang-Seok Kang

发明人： Kee-Won Kwon ,  Chang-Seok Kang

IPC分类号： H01L27/04 ,  H01L21/02 ,  H01L21/822 ,  H01L21/8242 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/10 ,  H01L27/105 ,  H01L27/108 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792 ,  H01L21/00 ,  H01L21/20

CPC分类号： H01L27/11502 ,  H01L27/10808 ,  H01L27/10852 ,  H01L28/55 ,  H01L28/60

摘要： In a semiconductor device having a ferroelectric capacitor and manufacturing method thereof, a spacer comprising a low dielectric constant material is formed on the side surfaces of a plurality of lower electrodes separated into each cell unit, and a ferroelectric film is formed on the lower electrodes whereon the low dielectric constant material spacer is formed, and an upper electrode is formed on the ferroelectric film, to thereby prevent an error which may be caused between the adjacent lower electrodes.

摘要翻译： 在具有铁电电容器的半导体装置及其制造方法中，在分离成各电池单元的多个下电极的侧面形成有包含低介电常数材料的间隔物，在下电极上形成强电介质膜 形成低介电常数材料间隔物，并且在铁电体膜上形成上电极，从而防止在相邻的下电极之间可能引起的误差。