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公开(公告)号：US08711650B2
公开(公告)日：2014-04-29
申请号：US13533003
申请日：2012-06-26
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C8/00
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。
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公开(公告)号：US06847575B2
公开(公告)日：2005-01-25
申请号：US10411237
申请日：2003-04-11
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C11/41 , G11C5/00 , G11C8/12 , G11C11/00 , G11C11/401 , G11C11/403 , G11C11/406 , G11C11/407 , G11C16/04 , H01L25/04 , H01L25/065 , H01L25/07 , H01L25/18 , G11C8/00
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。
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公开(公告)号：US06411561B1
公开(公告)日：2002-06-25
申请号：US09897503
申请日：2001-07-03
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C700
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
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公开(公告)号：US08400853B2
公开(公告)日：2013-03-19
申请号：US12778120
申请日：2010-05-12
IPC分类号： G11C7/00
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.
摘要翻译： 提供了一种修复电路，实现混合多种修复方法的组修复和用于制作商品边缘的修复设计方法。 在安装多个RAM的芯片中，提供了考虑到芯片产量和面积增加的权衡以及安装修复电路的修复电路和修复设计方法。 修复电路分别实现了可以选择修复电路的存在的混合多种修复方法的组修复，以及在修复电路是否在芯片中的RAMS时分别从I / O，列和行修复中的一种或多种修复方法 安装。 修复电路通过将安装修复电路的RAM分类为多个RAM组来对每个RAM组进行修复。 此外，提供了使晶片中获得的多个芯片的数量的修复方法和RAM分组方法的估计方法。
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公开(公告)号：US20100290299A1
公开(公告)日：2010-11-18
申请号：US12778120
申请日：2010-05-12
CPC分类号： G11C29/44 , G11C29/4401 , G11C29/88
摘要： A repair circuit achieving “group repair of mixed multiple repair methods” and a repair design method for making a product margin suitable are provided. In a chip mounting multiple RAMs, a repair circuit and a repair design method in consideration of a trade-off of chip yield and area increase along with mounting a repair circuit are provided. A repair circuit achieving “group repair of mixed multiple repair methods” which can select existence of a repair circuit, and one or more repair methods from I/O, column, and row repairs on the RAMS in the chip, respectively, when a repair circuit is mounted. The repair circuit performs repair per RAM group by sorting the RAMs mounting a repair circuit into a plurality of RAM groups. Also, a repair method which makes a number of acquired good chips in a wafer and an estimation method of the RAM grouping method are provided.
摘要翻译： 提供了实现“混合多重修复方法的组修复”的维修电路和用于制造商品边缘的修理设计方法。 在安装多个RAM的芯片中，提供了考虑到芯片产量和面积增加的权衡以及安装修复电路的修复电路和修复设计方法。 分别在芯片上的RAMS上实现“可以选择修复电路的存在的”混合多重修复方法的组修复“以及I / O，列和行修复中的一种或多种修复方法的修复电路 电路安装。 修复电路通过将安装修复电路的RAM分类为多个RAM组来对每个RAM组进行修复。 此外，提供了使晶片中获得的多个芯片的数量的修复方法和RAM分组方法的估计方法。
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公开(公告)号：US07554872B2
公开(公告)日：2009-06-30
申请号：US11037088
申请日：2005-01-19
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C8/00
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
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公开(公告)号：US06392950B2
公开(公告)日：2002-05-21
申请号：US09803958
申请日：2001-06-29
申请人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
发明人： Kazushige Ayukawa , Seiji Miura , Yoshikazu Saitou
IPC分类号： G11C800
CPC分类号： G11C11/005 , G11C5/04 , G11C5/06 , G11C5/063 , G11C5/143 , G11C8/12 , G11C11/406 , G11C11/40607 , G11C11/40618 , G11C11/4076 , H01L2224/06145 , H01L2224/06156 , H01L2224/32145 , H01L2224/48091 , H01L2224/48137 , H01L2224/48139 , H01L2224/48227 , H01L2924/01039 , H01L2924/01055 , H01L2924/13091 , H01L2924/14 , H01L2924/1433 , H01L2924/15311 , H01L2924/19041 , H01L2924/3025 , H01L2924/00014 , H01L2924/00
摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.
摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。
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