公开(公告)号：US20090245004A1

公开(公告)日：2009-10-01

申请号：US12482579

申请日：2009-06-11

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C7/00 ,  G11C8/00

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

公开(公告)号：US06928512B2

公开(公告)日：2005-08-09

申请号：US10163364

申请日：2002-06-06

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Tetsuya Iwamura ,  Kouichi Hoshi ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Tetsuya Iwamura ,  Kouichi Hoshi ,  Yoshikazu Saitou

IPC分类号： G11C11/41 ,  G06F12/00 ,  G06F12/06 ,  G11C5/00 ,  G11C11/00 ,  G11C11/401 ,  G11C11/406 ,  G11C11/408

CPC分类号： G11C11/4087 ,  G11C11/005 ,  G11C11/406 ,  G11C2207/2245 ,  H01L25/0652 ,  H01L25/0655 ,  H01L2224/06135 ,  H01L2224/06156 ,  H01L2224/48137 ,  H01L2224/48145 ,  H01L2224/48227 ,  H01L2224/49175 ,  H01L2924/13091 ,  H01L2924/15311 ,  H01L2924/3025 ,  H01L2924/00 ,  H01L2924/00012

摘要： A non-volatile memory, an SRAM, a DRAM and a control circuit are module-formed into a single packaged. The control circuit assigns addresses to the SRAM and addresses to the DRAM and data necessary to be held for a long period of time is saved in the SRAM. Two chips of DRAM are mapped to the same address space and refreshed alternately. The plural chips are arranged such that they are mutually laminated, and they are wired by means of a BGA or inter-chip bonding.

摘要翻译： 非易失性存储器，SRAM，DRAM和控制电路被模块化成单个封装。 控制电路将地址分配给SRAM，并将DRAM的地址分配给SRAM，并将需要长时间保持的数据保存在SRAM中。 DRAM的两个芯片映射到相同的地址空间并交替刷新。 多个芯片被布置为使得它们相互层压，并且它们通过BGA或芯片间接合来布线。

公开(公告)号：US20120262992A1

公开(公告)日：2012-10-18

申请号：US13533003

申请日：2012-06-26

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C16/04

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

公开(公告)号：US08223578B2

公开(公告)日：2012-07-17

申请号：US12482579

申请日：2009-06-11

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C5/06

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

公开(公告)号：US20050128853A1

公开(公告)日：2005-06-16

申请号：US11037088

申请日：2005-01-19

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C11/41 ,  G11C5/00 ,  G11C8/12 ,  G11C11/00 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C16/04 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  G11C8/00

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

公开(公告)号：US06587393B2

公开(公告)日：2003-07-01

申请号：US10140945

申请日：2002-05-09

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C800

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

公开(公告)号：US08711650B2

公开(公告)日：2014-04-29

申请号：US13533003

申请日：2012-06-26

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C8/00

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

公开(公告)号：US06847575B2

公开(公告)日：2005-01-25

申请号：US10411237

申请日：2003-04-11

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C11/41 ,  G11C5/00 ,  G11C8/12 ,  G11C11/00 ,  G11C11/401 ,  G11C11/403 ,  G11C11/406 ,  G11C11/407 ,  G11C16/04 ,  H01L25/04 ,  H01L25/065 ,  H01L25/07 ,  H01L25/18 ,  G11C8/00

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

摘要翻译： 为了实现具有大的存储容量和减少的数据保持电流的存储器，非易失性存储器，SRAM，DRAM和控制电路被模块化成一个封装。 控制电路对SRAM和DRAM进行地址分配，并将要长时间保留的数据存储在SRAM中。 在DRAM中，多个存储体被分成两组，映射到相同的地址空间，并且交替地刷新集合。 它们的多个芯片被堆叠和布置，并且通过使用BGA和芯片到芯片的接合进行布线。

公开(公告)号：US06411561B1

公开(公告)日：2002-06-25

申请号：US09897503

申请日：2001-07-03

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C700

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.

公开(公告)号：US07554872B2

公开(公告)日：2009-06-30

申请号：US11037088

申请日：2005-01-19

申请人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

发明人： Kazushige Ayukawa ,  Seiji Miura ,  Yoshikazu Saitou

IPC分类号： G11C8/00

CPC分类号： G11C11/005 ,  G11C5/04 ,  G11C5/06 ,  G11C5/063 ,  G11C5/143 ,  G11C8/12 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40618 ,  G11C11/4076 ,  H01L2224/06145 ,  H01L2224/06156 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48137 ,  H01L2224/48139 ,  H01L2224/48227 ,  H01L2924/01039 ,  H01L2924/01055 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/1433 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/3025 ,  H01L2924/00014 ,  H01L2924/00

摘要： In order to implement a memory having a large storage capacity and a reduced data retention current, a non-volatile memory, an SRAM, a DRAM, and a control circuit are modularized into one package. The control circuit conducts assignment of addresses to the SRAM and DRAM, and stores data that must be retained over a long period of time in the SRAM. In the DRAM, a plurality of banks are divided into two sets, and mapped to the same address space, and sets are refreshed alternately. A plurality of chips of them are stacked and disposed, and wired by using the BGA and chip-to-chip bonding.