公开(公告)号：US08952445B2

公开(公告)日：2015-02-10

申请号：US13601372

申请日：2012-08-31

申请人： Masayuki Tanaka ,  Kazuhiro Matsuo

发明人： Masayuki Tanaka ,  Kazuhiro Matsuo

IPC分类号： H01L29/792 ,  H01L21/28 ,  H01L27/115

CPC分类号： H01L29/792 ,  H01L21/28273 ,  H01L27/11521

摘要： According to one embodiment, a nonvolatile semiconductor memory device has a semiconductor substrate, a first insulating film formed on the semiconductor substrate, a charge storage film formed on the first insulating film, a second insulating film formed on the charge storage film, and a control electrode formed on the second insulating film. In the nonvolatile semiconductor memory device, the second insulating film has a laminated structure that has a first silicon oxide film, a first silicon nitride film, and a second silicon oxide film, a first atom is provided at an interface between the first silicon oxide film and the first silicon nitride film, and/or at an interface between the second silicon oxide film and the first silicon nitride film, and the first atom is selected from the group consisting of aluminum, boron, and alkaline earth metals.

摘要翻译： 根据一个实施例，非易失性半导体存储器件具有半导体衬底，形成在半导体衬底上的第一绝缘膜，形成在第一绝缘膜上的电荷存储膜，形成在电荷存储膜上的第二绝缘膜，以及控制 电极形成在第二绝缘膜上。 在非易失性半导体存储器件中，第二绝缘膜具有层叠结构，该叠层结构具有第一氧化硅膜，第一氮化硅膜和第二氧化硅膜，第一原子设置在第一氧化硅膜 和/或在第二氧化硅膜和第一氮化硅膜之间的界面处，并且第一原子选自铝，硼和碱土金属。

公开(公告)号：US08941168B2

公开(公告)日：2015-01-27

申请号：US13423633

申请日：2012-03-19

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

IPC分类号： H01L29/788 ,  H01L29/423 ,  H01L21/28 ,  H01L27/115 ,  H01L29/66 ,  H01L21/762

CPC分类号： H01L29/42324 ,  H01L21/28273 ,  H01L21/76232 ,  H01L27/11521 ,  H01L29/66825 ,  H01L29/7881

摘要： A semiconductor device includes an element isolation region having an element isolation insulating film therein; an active region delineated by the element isolation region; agate insulating film formed in the active region; a charge storage layer above the gate insulating film; and an interelectrode insulating film. The interelectrode insulating film is formed in a first region above an upper surface of the element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a stack of a first silicon oxide film, a first silicon nitride film, a second silicon oxide film, and a second silicon nitride film. A control electrode layer is formed above the interelectrode insulating film. The second silicon oxide film is thinner in the first region than in the third region.

摘要翻译： 半导体器件包括其中具有元件隔离绝缘膜的元件隔离区域; 由元件隔离区域划定的活动区域; 形成在活性区域中的玛瑙绝缘膜; 栅极绝缘膜上方的电荷存储层; 和电极间绝缘膜。 电极间绝缘膜形成在元件隔离绝缘膜的上表面上方的第一区域，沿着电荷存储层的侧壁的第二区域和电荷存储层的上表面上方的第三区域。 电极间绝缘膜包括第一氧化硅膜，第一氮化硅膜，第二氧化硅膜和第二氮化硅膜的堆叠。 在电极间绝缘膜的上方形成控制电极层。 第二氧化硅膜在第一区域比在第三区域薄。

公开(公告)号：US20110298039A1

公开(公告)日：2011-12-08

申请号：US13207149

申请日：2011-08-10

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

IPC分类号： H01L29/792 ,  H01L29/78

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer, and a control electrode formed on the second insulation layer. The second insulation layer includes a first silicon oxide film formed above the charge storage layer, a silicon nitride film formed on the first silicon oxide film, a metal oxide film formed on the silicon nitride film, and a nitride film formed on the metal oxide film. The metal oxide film has a relative permittivity of not less than 7.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层和形成在第二绝缘层上的控制电极 绝缘层。 第二绝缘层包括在电荷存储层上形成的第一氧化硅膜，形成在第一氧化硅膜上的氮化硅膜，形成在氮化硅膜上的金属氧化物膜，以及形成在金属氧化物膜上的氮化物膜 。 金属氧化物膜的相对介电常数不小于7。

公开(公告)号：US08742487B2

公开(公告)日：2014-06-03

申请号：US13207149

申请日：2011-08-10

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Takeo Furuhata ,  Koji Nakahara

IPC分类号： H01L29/792

CPC分类号： H01L29/792 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11568 ,  H01L29/513 ,  H01L29/7881

摘要： A nonvolatile semiconductor memory device includes a semiconductor substrate, a first insulation layer formed on the semiconductor substrate, a charge storage layer formed on the first insulation layer, a second insulation layer formed on the charge storage layer and including a first high dielectric insulating film which has a higher relative permittivity than a silicon nitride film and a second high dielectric insulating film which has a higher relative permittivity than a silicon nitride film, the first and second high dielectric insulating films being structured so that a silicon oxide film is interposed between them, a control electrode formed on the second insulation layer, a first portion formed between the charge storage layer and the second insulation layer and containing silicon and nitrogen, and a second portion containing silicon and oxygen and located between the charge storage layer and the second insulation layer.

摘要翻译： 非易失性半导体存储器件包括半导体衬底，形成在半导体衬底上的第一绝缘层，形成在第一绝缘层上的电荷存储层，形成在电荷存储层上的第二绝缘层，并且包括第一高介电绝缘膜， 具有比氮化硅膜更高的相对介电常数的相对介电常数和比氮化硅膜具有更高的相对介电常数的第二高介电绝缘膜，第一和第二高介电绝缘膜被构造成在它们之间插入氧化硅膜， 形成在所述第二绝缘层上的控制电极，形成在所述电荷存储层和所述第二绝缘层之间并且包含硅和氮的第一部分，以及位于所述电荷存储层和所述第二绝缘层之间的含有硅和氧的第二部分 。

公开(公告)号：US08471326B2

公开(公告)日：2013-06-25

申请号：US13049573

申请日：2011-03-16

申请人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka

发明人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka

IPC分类号： H01L21/762 ,  H01L27/115

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

摘要： According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.

摘要翻译： 根据一个实施例，半导体衬底包括单元区域和外围电路区域，在单元区域和外围电路区域中的半导体衬底上形成第一电介质膜，在第一电介质膜上形成第一导电膜 单元区域和外围电路区域，在单元区域中的第一导电膜上形成第一导电膜电介质膜，在外围电路的第一导电膜上形成第二导电膜电介质膜 区域，其膜厚度大于第一导电膜电介质膜，并且第二导电膜形成在电池区域中的第一导电膜电介质膜上，第二导电膜电介质膜 在外围电路区域。

公开(公告)号：US20130069135A1

公开(公告)日：2013-03-21

申请号：US13423664

申请日：2012-03-19

申请人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

发明人： Koji Nakahara ,  Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

IPC分类号： H01L29/788 ,  H01L21/336

CPC分类号： H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

摘要： A semiconductor device includes an interelectrode insulating film formed between a charge storage layer and a control electrode layer. The interelectrode insulating film is formed in a first region above an upper surface of an element isolation insulating film, a second region along a sidewall of the charge storage layer, and a third region above an upper surface of the charge storage layer. The interelectrode insulating film includes a first stack including a first silicon nitride film or a high dielectric constant film interposed between a first and a second silicon oxide film or a second stack including a second high dielectric constant film and a third silicon oxide film, and a second silicon nitride film formed between the control electrode layer and the first or the second stack. The second silicon nitride film is relatively thinner in the third region than in the first region.

摘要翻译： 半导体器件包括在电荷存储层和控制电极层之间形成的电极间绝缘膜。 电极间绝缘膜形成在元件隔离绝缘膜的上表面上方的第一区域，沿着电荷存储层的侧壁的第二区域和电荷存储层的上表面上方的第三区域。 电极间绝缘膜包括：第一堆叠，其包括介于第一和第二氧化硅膜之间的第一氮化硅膜或高介电常数膜，或包括第二高介电常数膜和第三氧化硅膜的第二堆叠， 形成在控制电极层和第一或第二堆叠之间的第二氮化硅膜。 在第三区域中，第二氮化硅膜比第一区域相对薄。

公开(公告)号：US20120049258A1

公开(公告)日：2012-03-01

申请号：US13049573

申请日：2011-03-16

申请人： Koji NAKAHARA ,  Kazuhiro Matsuo ,  Masayuki Tanaka

发明人： Koji NAKAHARA ,  Kazuhiro Matsuo ,  Masayuki Tanaka

IPC分类号： H01L29/788 ,  H01L21/762

CPC分类号： H01L27/11526 ,  H01L21/76224 ,  H01L27/11539 ,  H01L27/11541 ,  H01L27/11543

摘要： According to one embodiment, a semiconductor substrate includes a cell region and a peripheral circuit region, a first dielectric film is formed on the semiconductor substrate in the cell region and the peripheral circuit region, a first conductive film is formed on the first dielectric film in the cell region and the peripheral circuit region, a first inter-conductive-film dielectric film is formed on the first conductive film in the cell region, a second inter-conductive-film dielectric film is formed on the first conductive film in the peripheral circuit region and a film thickness thereof is larger than the first inter-conductive-film dielectric film, and a second conductive film is formed on the first inter-conductive-film dielectric film in the cell region and the second inter-conductive-film dielectric film in the peripheral circuit region.

摘要翻译： 根据一个实施例，半导体衬底包括单元区域和外围电路区域，在单元区域和外围电路区域中的半导体衬底上形成第一电介质膜，在第一电介质膜上形成第一导电膜 单元区域和外围电路区域，在单元区域中的第一导电膜上形成第一导电膜电介质膜，在外围电路的第一导电膜上形成第二导电膜电介质膜 区域，其膜厚度大于第一导电膜电介质膜，并且第二导电膜形成在电池区域中的第一导电膜电介质膜上，第二导电膜电介质膜 在外围电路区域。

公开(公告)号：US20110133267A1

公开(公告)日：2011-06-09

申请号：US12873857

申请日：2010-09-01

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

IPC分类号： H01L29/788 ,  H01L21/28

CPC分类号： H01L27/11521

摘要： A method of fabricating a semiconductor device includes forming a gate insulating film on a semiconductor substrate, forming a charge accumulation layer, an intermediate insulating film and a conductive layer sequentially on the gate insulating film, forming an electrode isolating trench in the conductive layer, the intermediate insulating film and the charge accumulation layer, forming a nitride film on upper and side surfaces of the conductive layer, side surfaces of the intermediate insulating film, side surfaces of the charge accumulation layer and an upper surface of the gate insulating film, removing the nitride film formed on the upper surface of the gate insulating film, and filling the electrode isolating trench with an insulating film.

摘要翻译： 一种制造半导体器件的方法包括在半导体衬底上形成栅极绝缘膜，在栅极绝缘膜上依次形成电荷累积层，中间绝缘膜和导电层，在导电层中形成电极隔离沟槽， 中间绝缘膜和电荷累积层，在导电层的上表面和侧表面，中间绝缘膜的侧表面，电荷累积层的侧表面和栅极绝缘膜的上表面上形成氮化物膜， 形成在栅极绝缘膜的上表面上的氮化物膜，并且用绝缘膜填充电极隔离沟槽。

公开(公告)号：US08471319B2

公开(公告)日：2013-06-25

申请号：US13237486

申请日：2011-09-20

申请人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

发明人： Kazuhiro Matsuo ,  Masayuki Tanaka ,  Hirofumi Iikawa

IPC分类号： H01L29/792 ,  H01L21/28

CPC分类号： H01L27/11521 ,  H01L21/28273 ,  H01L29/513 ,  H01L29/7883

摘要： A semiconductor device is disclosed. The semiconductor device includes a semiconductor substrate; a gate insulating film formed above the semiconductor substrate; a charge storage layer formed above the gate insulating film; a multilayered interelectrode insulating film formed in a first region above an upper surface portion of the element isolation insulating film, a second region above a sidewall portion of the charge storage layer and a third region above an upper surface portion of the charge storage layer, the interelectrode insulating film including a stack of an upper silicon oxide film, a middle silicon nitride film, and a lower silicon oxide film; a control gate electrode formed above the interelectrode insulating film; wherein the middle silicon nitride film is thinner in the third region than in the second region and the upper silicon oxide film is thicker in the third region than in the second region.

摘要翻译： 公开了一种半导体器件。 半导体器件包括半导体衬底; 形成在所述半导体衬底上的栅极绝缘膜; 形成在栅极绝缘膜上方的电荷存储层; 形成在元件隔离绝缘膜的上表面部分上方的第一区域中的多层电极间绝缘膜，电荷存储层的侧壁部分上方的第二区域和电荷存储层的上表面部分上方的第三区域， 电极间绝缘膜，其包括上氧化硅膜，中间氮化硅膜和下氧化硅膜的堆叠; 形成在电极间绝缘膜之上的控制栅电极; 其中中间氮化硅膜在第三区域比第二区域薄，上部氧化硅膜在第三区域比第二区域厚。

公开(公告)号：US08304352B2

公开(公告)日：2012-11-06

申请号：US13051031

申请日：2011-03-18

申请人： Masayuki Tanaka ,  Kazuhiro Matsuo ,  Yoshio Ozawa

发明人： Masayuki Tanaka ,  Kazuhiro Matsuo ,  Yoshio Ozawa

IPC分类号： H01L21/31 ,  H01L21/469

CPC分类号： H01L21/28282 ,  H01L27/11568 ,  H01L27/11582

摘要： According to an embodiment, there is provided a method of manufacturing a semiconductor device, including forming a nitride film by nitriding a surface of an underlying region having a semiconductor region containing silicon as a main component and an insulating region containing silicon and oxygen as a main component and adjacent to the semiconductor region, carrying out oxidation with respect to the nitride film to convert a portion of the nitride film which is formed on the insulating region into an oxide film and to leave a portion of the nitride film which is formed on the semiconductor region as at least part of a charge storage insulating film, forming a block insulating film on the charge storage insulating film, and forming a gate electrode film on the block insulating film.

摘要翻译： 根据一个实施例，提供一种制造半导体器件的方法，包括通过氮化作为主要成分的含有硅的半导体区域的下面的区域的表面和以硅和氧为主要的绝缘区域来形成氮化物膜 并且与半导体区域相邻，相对于氮化物膜进行氧化，将形成在绝缘区域上的氮化物膜的一部分转换为氧化膜，并且使形成在该半导体层上的氮化膜的一部分 半导体区域作为电荷存储绝缘膜的至少一部分，在电荷存储绝缘膜上形成块绝缘膜，并在块绝缘膜上形成栅极电极膜。