公开(公告)号：US20130289187A1

公开(公告)日：2013-10-31

申请号：US13880186

申请日：2011-10-18

Applicant: Masahiro Wada ,  Ken Ukawa ,  Kenji Yoshida ,  Yusuke Tanaka

Inventor： Masahiro Wada ,  Ken Ukawa ,  Kenji Yoshida ,  Yusuke Tanaka

IPC: H01B3/40

CPC classification number: H01B3/40 ,  C08G59/621 ,  H01L23/295 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49582 ,  H01L24/45 ,  H01L24/48 ,  H01L24/73 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/45015 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48247 ,  H01L2224/73265 ,  H01L2924/01019 ,  H01L2924/01079 ,  H01L2924/10253 ,  H01L2924/12041 ,  H01L2924/1301 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00011 ,  H01L2924/00012 ,  H01L2924/20752

Abstract: A resin composition for encapsulation according to the present invention includes: a phenol resin-based curing agent (A) essentially containing a polymer component (A-1) in which a biphenylene group-containing structural unit bonds a monovalent hydroxyphenylene structural unit and a polyvalent hydroxyphenylene structural unit together and a polymer component (A-2) in which the biphenylene group-containing structural unit bonds the polyvalent hydroxyphenylene structural units together; an epoxy resin (B); and an inorganic filler (C). This makes it possible to economically obtain a resin composition for encapsulation having soldering resistance, flame resistance, continuous moldability, flowability and high temperature storage stability in an excellent balanced manner, and an electronic component device produced by encapsulating an element with a cured product thereof and having high reliability.

Abstract translation: 根据本发明的用于封装的树脂组合物包括：基本上含有其中含联苯基的结构单元与一价羟基亚苯基结构单元和多价基团结合的聚合物组分（A-1）的酚醛树脂基固化剂（A） 羟基亚苯基结构单元以及含有亚联苯基的结构单元将多价羟基亚苯基结构单元结合在一起的聚合物组分（A-2） 环氧树脂（B）; 和无机填料（C）。 这使得可以以优异的平衡方式经济地获得具有耐焊接性，阻燃性，连续成型性，流动性和高温储存稳定性的封装用树脂组合物，以及通过用固化物包封元件而制造的电子部件装置， 具有高可靠性。

公开(公告)号：US08556266B2

公开(公告)日：2013-10-15

申请号：US12521669

申请日：2007-12-28

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: A63F9/24 ,  G06K7/14

CPC classification number: A63F1/04 ,  A63F1/02 ,  A63F2009/062 ,  A63F2009/2419 ,  A63F2250/602

Abstract: A flexible card which allows data of the card to be changed with a simple operation is provided, thereby permitting users to sustain interest in the card and a relevant game. The card comprises a first dot pattern in which a coordinate value or a code value is patterned and which is recognizable by predetermined irradiation light at least on one surface thereof and a second dot pattern which is patterned in a predetermined algorithm in a region overlapping with a region where the first dot pattern is provided or a region different from a region where the first dot pattern is provided.

Abstract translation: 提供允许以简单操作改变卡的数据的灵活的卡，从而允许用户维持对卡的兴趣和相关游戏。 该卡片包括第一点阵图形，其中坐标值或代码值被图案化，并且其至少在其一个表面上可被预定的照射光识别，而第二点阵图案以预定的算法在与 设置第一点图形的区域或与设置第一点图案的区域不同的区域。

公开(公告)号：US08488264B2

公开(公告)日：2013-07-16

申请号：US13237757

申请日：2011-09-20

Applicant: Kenji Yoshida ,  Akihiro Yamazaki

Inventor： Kenji Yoshida ,  Akihiro Yamazaki

IPC: G11B5/09

CPC classification number: G11B5/59688 ,  G11B5/59655

Abstract: According to one embodiment, a signal processing circuit processes a signal read from a magnetic disk including a servo region and a user data region, the servo region including a servo address mark, the user data region including a data sector, and includes a counter and a gate controller. The counter is configured to count a first clock when having detected the servo address mark based on the signal read from the magnetic disk. The gate controller is configured to generate a pulse for locating the data sector in synchronization with a second clock when the counter counts a first value.

Abstract translation: 根据一个实施例，信号处理电路处理从包括伺服区域和用户数据区域的磁盘读取的信号，所述伺服区域包括伺服地址标记，所述用户数据区域包括数据扇区，并且包括计数器和 门控制器 该计数器被配置为基于从磁盘读取的信号检测到伺服地址标记来对第一时钟进行计数。 门控制器被配置为当计数器计数第一值时，与第二时钟同步地产生用于定位数据扇区的脉冲。

公开(公告)号：US08395439B2

公开(公告)日：2013-03-12

申请号：US12923166

申请日：2010-09-07

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: G05F1/10

CPC classification number: G11C7/1072 ,  G11C5/147 ,  G11C7/20 ,  G11C11/4072 ,  G11C11/4074 ,  G11C29/02 ,  G11C29/021 ,  G11C29/028

Abstract: An internal voltage adjusting circuit of a semiconductor memory device processes a period from activation to deactivation of a reset bar signal by dividing the period into a first period to a third period. In the first period, a peripheral circuit voltage is stabilized to a lowest value to suppress power consumption. In the second period in which a power source voltage is stabilized, the peripheral circuit voltage is set to a highest value to read out optimum internal voltage values from a fuse circuit in a stable manner. In the third period after reading out the optimum internal voltage values, the peripheral circuit voltage is returned to the lowest value to suppress the power consumption. When the reset bar signal is deactivated, the peripheral circuit voltage is set based on the optimum internal voltage values read out from the fuse circuit.

Abstract translation: 半导体存储器件的内部电压调整电路通过将该周期划分为第一周期至第三周期来处理从复位条信号的激活到去激活的周期。 在第一期间，外围电路电压稳定在最低值以抑制功耗。 在电源电压稳定的第二时段中，将外围电路电压设定为最高值，以稳定的方式从熔丝电路读出最佳的内部电压值。 在读出最佳内部电压值的第三个周期中，外围电路电压返回到最低值以抑制功耗。 当复位条信号被去激活时，根据从熔丝回路读出的最佳内部电压值设定外围电路电压。

公开(公告)号：US08363277B2

公开(公告)日：2013-01-29

申请号：US13448701

申请日：2012-04-17

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: G06F15/00 ,  G06K1/00 ,  H04N1/60 ,  G06F3/12

CPC classification number: G06K19/06037 ,  B41M3/144 ,  B42D25/29

Abstract: With the aim of realizing an easy and inexpensive method of realizing a “stealth” dot pattern, whose presence on a medium surface is not visually recognizable, merely through minor improvements in the existing printing technology, the present invention provides dots which form a dot pattern by printing these dots using an ink of any color reactive in the infrared or ultraviolet wavelength range on a medium surface on which a dot pattern is to be formed, for use with a dot pattern reading system that irradiates infrared or ultraviolet light on a medium surface having a dot pattern provided thereon, recognizes the dot pattern by reading the reflections of the light with an optical reading means, converts the dot pattern into the corresponding data, and outputs the text, voice, images and so forth contained in the data.

Abstract translation: 为了实现一种容易且廉价的实现隐形点阵图案的方法，其在中等表面上的存在不能在视觉上被识别，仅通过现有打印技术的微小改进，本发明提供了通过打印形成点图案的点 这些点使用在要形成点图形的介质表面上的在红外或紫外线波长范围内具有反应性的任何颜色的墨，用于在具有红色或紫外线波长范围的介质表面上照射红外线或紫外光的点阵图形读取系统 设置在其上的点图案通过用光学读取装置读取光的反射来识别点图案，将点图案转换成对应的数据，并输出数据中包含的文本，声音，图像等。

公开(公告)号：US08291304B2

公开(公告)日：2012-10-16

申请号：US13088957

申请日：2011-04-18

Applicant: Kenji Yoshida ,  Haruka Obata ,  Kohsuke Harada

Inventor： Kenji Yoshida ,  Haruka Obata ,  Kohsuke Harada

IPC: H03M13/03

CPC classification number: G11B20/10009 ,  G11B20/10055 ,  G11B20/10296 ,  G11B20/10509 ,  G11B2220/2516 ,  H03M13/2957 ,  H03M13/3905 ,  H03M13/4138 ,  H03M13/6306 ,  H03M13/6343

Abstract: According to one embodiment, a signal processing device comprises a first waveform equalizer, a second waveform equalizer, a first Viterbi decoder, a second Viterbi decoder. The first and the second waveform equalizers equalize a waveform of the input signal according to first and second partial response characteristics and output first and second partial response signals. The first and second Viterbi decoders decode the first and the second partial response signals by means of Viterbi decoding process. The input signal is reproduced based on an output of the first Viterbi decoder and an output of the second Viterbi decoder.

Abstract translation: 根据一个实施例，信号处理装置包括第一波形均衡器，第二波形均衡器，第一维特比解码器，第二维特比译码器。 第一和第二波形均衡器根据第一和第二部分响应特性对输入信号的波形进行均衡，并输出第一和第二部分响应信号。 第一和第二维特比解码器通过维特比解码处理解码第一和第二部分响应信号。 基于第一维特比解码器的输出和第二维特比解码器的输出再现输入信号。

公开(公告)号：US20120110416A1

公开(公告)日：2012-05-03

申请号：US13174596

申请日：2011-06-30

Applicant: Yosuke KONDO ,  Kenji Yoshida

Inventor： Yosuke KONDO ,  Kenji Yoshida

IPC: H03M13/19 ,  G06F11/10

CPC classification number: H03M13/19 ,  H03M13/616 ,  H03M13/618 ,  H03M13/6575

Abstract: According to one embodiment, an encoder/decoder apparatus includes an encoder module, a decoder module, and a transposing module. The encoder module is configured to generate a Hamming code from the input data, in accordance with a check matrix having a specific regularity. The decoder module is configured to detect an error position in the output data composed of the Hamming code, in accordance with the check matrix. The transposing module is configured to perform a transposing process of transposing some of the columns of the check matrix, while maintaining the regularity of the check matrix, and to change the error position in accordance with the transposing process, during the decoding process.

Abstract translation: 根据一个实施例，编码器/解码器装置包括编码器模块，解码器模块和转置模块。 编码器模块被配置为根据具有特定规则性的校验矩阵从输入数据生成汉明码。 解码器模块被配置为根据校验矩阵来检测由汉明码组成的输出数据中的错误位置。 移调模块被配置为执行转置处理，以便在维持校验矩阵的规律性的同时，在校验矩阵的一些列转置，并且在解码过程期间根据转置处理改变错误位置。

公开(公告)号：US08089226B2

公开(公告)日：2012-01-03

申请号：US12605373

申请日：2009-10-26

Applicant: Ryuta Matsutani ,  Kenji Yoshida ,  Shigeru Sakurai

Inventor： Ryuta Matsutani ,  Kenji Yoshida ,  Shigeru Sakurai

IPC: H02P5/46

CPC classification number: B25B21/00 ,  B23P19/066 ,  B25B23/14

Abstract: A torque control device controlling torque of first and second mechanical units connected coaxially to each other through connecting members includes a controller generating first and second references from a command from a host system, first and second motors respectively driving the first and second mechanical units, first and second motor control units respectively controlling the first and second motors on the basis of the first and second references. The first and second references synchronously accelerate the first and second motors to first rotational speed, then increase rotational speed of the second motor according to a speed profile to produce torsional torque in the connecting members, decelerate the second motor to the first rotational speed after the torsional torque reaches a predetermined value, and synchronously decelerate and stop the first and second motors after a predetermined time period elapses.

Abstract translation: 控制通过连接构件彼此同轴连接的第一和第二机械单元的扭矩的转矩控制装置包括控制器，其根据来自主机系统的命令产生第一和第二参考，第一和第二电动机分别驱动第一和第二机械单元，第一 以及第二电动机控制单元，其基于第一和第二参考分别控制第一和第二电动机。 第一和第二参考同步地将第一和第二电动机加速到第一转速，然后根据速度曲线提高第二电动机的转速，以在连接构件中产生扭转扭矩，在第二电动机之后将第二电动机减速到第一转速 扭转扭矩达到预定值，并且在经过预定时间段之后同步地减速和停止第一和第二电动机。

公开(公告)号：US08069025B2

公开(公告)日：2011-11-29

申请号：US12252362

申请日：2008-10-16

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: G06F17/50 ,  G06F13/00

CPC classification number: G06F17/5022

Abstract: According to one embodiment, a logical circuit to be simulated includes a timing network and a specific logical device. The timing network transmits a logical value change of an input signal in correspondence with an elapse of time or clock number increments. The specific logical device receives a timing network output signal that appears at an exit node of the timing network, and a logical value change or a logical value after change of the clock. When predetermined constraint information represents a constraint that a time period or the demanded number of clock cycles needed for a transition of a signal level change to pass through a signal path in the timing network is equal to or smaller than a predetermined numerical value (or equal to or larger than a predetermined numerical value), it is checked if the signal input to the specific logical device violates the predetermined constraint information.

Abstract translation: 根据一个实施例，待仿真的逻辑电路包括定时网络和特定的逻辑设备。 定时网络与时间或时钟数增量相对应地传送输入信号的逻辑值变化。 特定逻辑设备接收出现在定时网络的出口节点处的定时网络输出信号，以及在时钟变化之后的逻辑值改变或逻辑值。 当预定的约束信息表示时间周期或信号电平转换所需要的时钟周期数量改变以通过定时网络中的信号路径的约束等于或小于预定数值（或相等） 达到或大于预定数值），检查输入到特定逻辑设备的信号是否违反预定约束信息。

公开(公告)号：US08031375B2

公开(公告)日：2011-10-04

申请号：US11912597

申请日：2005-04-28

Applicant: Kenji Yoshida

Inventor： Kenji Yoshida

IPC: H04N1/40 ,  G06K15/00 ,  G06K15/10

CPC classification number: G06K7/1417 ,  G06K19/06037 ,  G06K2019/06234

Abstract: It is an object of the present invention to provide an information input/output method that is capable of imparting different functions to dots of a dot pattern displayed on a printed matter, thereby, at the time of providing information from the dot pattern, recognizing directivity and speedily providing information and that is capable of checking an error relative to a dot layout state, and further, that is capable of enhancing security. Therefore, according to the present invention, the information input/output method is provided, and includes: defining as a block a rectangular area of a square or a rectangle, of a medium face such as a printed matter; while a straight line in a vertical direction and a horizontal direction configuring a frame of the block is defined as a standard grid line, providing a virtual reference grid point by predetermined interval on the reference grid line; laying out a reference grid point dot on a virtual reference grid point; connecting the virtual reference grid points to each other and defining a straight line parallel to the reference grid line as a grid line; defining a cross point between the grid lines as a virtual grid point; generating a dot pattern obtained by laying out one or a plurality of information dots, respectively, having a distance and a direction around the virtual grid point; reading such dot pattern as image information by optical reader means; numerically valuing the dot pattern; and reading and outputting information that corresponds to the numerically valued information from storage means.

Abstract translation: 本发明的目的是提供一种信息输入/输出方法，其能够对显示在打印物上的点阵图形的点赋予不同的功能，从而在从点图案提供信息时识别方向性 并且能够快速地提供信息，并且能够检查相对于点布局状态的错误，并且还能够增强安全性。 因此，根据本发明，提供信息输入/输出方法，并且包括：将诸如印刷品的中等面的矩形区域定义为矩形的矩形区域; 同时将构成该块的框架的垂直方向和水平方向的直线定义为标准网格线，在参考网格线上提供预定间隔的虚拟参考网格点; 在虚拟参考网格点上布置参考网格点; 将虚拟参考网格点彼此连接并且将与参考网格线平行的直线定义为网格线; 将网格线之间的交叉点定义为虚拟网格点; 生成分别具有围绕虚拟网格点的距离和方向布置一个或多个信息点而获得的点图案; 通过光学读取装置读取图像信息的点阵图形; 数值估价点图案; 以及从存储装置读取和输出与数值信息对应的信息。