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45 条记录 (耗时 0.028 秒)

    Methods for data redundancy across replaceable non-volatile memory storage devices
    11.
    发明授权
    Methods for data redundancy across replaceable non-volatile memory storage devices 有权
    可更换非易失性存储设备的数据冗余方法

    公开(公告)号：US08689042B1

    公开(公告)日：2014-04-01

    申请号：US13163581

    申请日：2011-06-17

    申请人： Ruban Kanapathippillai ,  Ashwin Narasimha ,  Kenneth A. Okin ,  Vijay Karamcheti

    发明人： Ruban Kanapathippillai ,  Ashwin Narasimha ,  Kenneth A. Okin ,  Vijay Karamcheti

    IPC分类号： G06F11/00

    CPC分类号： G06F13/1694 ,  G06F13/1657 ,  Y02D10/14

    摘要： In one embodiment of the invention, a replaceable memory apparatus is disclosed. The replaceable memory apparatus includes a first rectangular multilayer printed circuit board having a first side and a second side opposite the first side; a first male pluggable electrical connector mounted to the first side near a first edge; a first female pluggable electrical connector mounted to the second side; and first non-volatile memory mounted to the first side and the second side. The first female pluggable electrical connector is coupled to the first male pluggable electrical connector to feed through first signals. The first non-volatile memory is coupled to the first female pluggable electrical connector and the first male pluggable electrical connector to receive the first signals.

    摘要翻译： 在本发明的一个实施例中，公开了一种可替换的存储装置。 可替换存储装置包括：第一矩形多层印刷电路板，具有第一侧和与第一侧相对的第二侧; 在第一边缘附近安装到第一侧的第一可插拔电连接器; 安装在第二侧的第一可插拔电插头; 以及安装到第一侧和第二侧的第一非易失性存储器。 第一可插拔电连接器可耦合到第一可插拔电连接器以馈送第一信号。 第一非易失性存储器耦合到第一可插拔电连接器和第一可插拔电连接器以接收第一信号。

    Managing memory systems containing components with asymmetric characteristics
    13.
    发明授权
    Managing memory systems containing components with asymmetric characteristics 有权
    管理包含具有不对称特征的组件的内存系统

    公开(公告)号：US08639901B2

    公开(公告)日：2014-01-28

    申请号：US13493766

    申请日：2012-06-11

    申请人： Kenneth A. Okin ,  Vijay Karamcheti

    发明人： Kenneth A. Okin ,  Vijay Karamcheti

    IPC分类号： G06F12/16

    CPC分类号： G06F12/02 ,  G06F11/1658 ,  G06F11/20 ,  G06F12/0246 ,  G06F12/06 ,  G06F12/08 ,  G06F12/10 ,  G06F2212/1032 ,  G06F2212/205 ,  G06F2212/7201 ,  G06F2212/7202 ,  G11C16/3418 ,  G11C16/3427

    摘要： A memory controller (MC) is associated with a remapping table to enable access to content in a memory system that includes asymmetric memory. The MC receives a request for a memory read or an Input/Output (I/O) write from a central processing unit (CPU) for a physical address specified by the system's memory management unit (MMU). The CPU uses the MMU to manage memory operations for the CPU, by translating the virtual addresses associated with CPU instructions into physical addresses representing system memory or I/O locations. The MC for asymmetric memories is configured to process the MMU-specified physical addresses as an additional type of virtual addresses, creating a layer of abstraction between the physical address specified by the MMU and the physical memory address with which that address is associated by the MC. The MC shields the CPU from the computational complexities required to implement a memory system with asymmetric components.

    摘要翻译： 存储器控制器（MC）与重映射表相关联，以使得能够访问包括非对称存储器的存储器系统中的内容。 MC从系统的存储器管理单元（MMU）指定的物理地址从中央处理单元（CPU）接收对存储器读取或输入/输出（I / O）写入的请求。 通过将与CPU指令关联的虚拟地址转换为表示系统内存或I / O位置的物理地址，CPU使用MMU来管理CPU的存储器操作。 用于非对称存储器的MC被配置为处理MMU指定的物理地址作为附加类型的虚拟地址，在MMU指定的物理地址与该地址由MC关联的物理存储器地址之间创建一个抽象层 。 MC屏蔽CPU免受实现具有不对称组件的存储系统所需的计算复杂性。

    TRANSLATING MEMORY MODULES FOR MAIN MEMORY
    16.
    发明申请
    TRANSLATING MEMORY MODULES FOR MAIN MEMORY 有权
    转换主存储器的存储器模块

    公开(公告)号：US20120079181A1

    公开(公告)日：2012-03-29

    申请号：US13311534

    申请日：2011-12-05

    申请人： Kenneth A. Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

    发明人： Kenneth A. Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F13/1668 ,  G06F2212/205 ,  Y02D10/14

    摘要： A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.

    摘要翻译： 公开了一种翻译存储器模块，其包括印刷电路板，耦合到印刷电路板的至少一个存储器集成电路以及耦合到印刷电路板并耦合在边缘连接器和至少一个存储器集成电路之间的至少一个支撑芯片 。 所述至少一个支持芯片包括用于在用于所述至少一个存储器集成电路的第一存储器通信协议和用于不同于所述第一存储器通信协议的存储器通道的第二存储器通信协议之间转换的双向转换器。 第二存储器通信协议，用于通过存储器通道总线传送数据，地址和控制信号，以将数据读取和写入到转换存储器模块的存储器中。

    Methods for a random read and read/write block accessible memory
    20.
    发明授权
    Methods for a random read and read/write block accessible memory 有权
    随机读取和写入块可访问存储器的方法

    公开(公告)号：US08745314B1

    公开(公告)日：2014-06-03

    申请号：US12490930

    申请日：2009-06-24

    申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

    发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy

    IPC分类号： G06F12/02

    CPC分类号： G06F12/0246 ,  G06F12/0866 ,  G06F13/1694 ,  G06F2212/211

    摘要： In one embodiment of the invention, a memory apparatus is disclosed. The memory apparatus includes a memory array, a block read/write controller, and a random access read memory controller. The memory array is block read/write accessible and random read accessible. The block read/write controller is coupled between the memory array and an external interconnect. The block read/write controller performs block read/write operations upon the memory array to access blocks of consecutive memory locations therein. The random access read memory controller is coupled between the memory array and the external interconnect in parallel with the block read/write access controller. The random access read memory controller performs random read memory operations upon the memory array to access random memory locations therein.

    摘要翻译： 在本发明的一个实施例中，公开了一种存储装置。 存储装置包括存储器阵列，块读/写控制器和随机存取读存储器控制器。 存储器阵列是块读/写可访问和随机读取可访问的。 块读/写控制器耦合在存储器阵列和外部互连之间。 块读/写控制器对存储器阵列执行块读/写操作，以访问其中的连续存储单元的块。 随机访问读存储器控制器与块读/写访问控制器并行地耦合在存储器阵列和外部互连之间。 随机存取读取存储器控制器对存储器阵列执行随机读取存储器操作以访问其中的随机存储器位置。