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    TRANSLATING MEMORY MODULES FOR MAIN MEMORY
    1.
    发明申请
    TRANSLATING MEMORY MODULES FOR MAIN MEMORY 有权
    转换主存储器的存储器模块

    公开(公告)号：US20120079181A1

    公开(公告)日：2012-03-29

    申请号：US13311534

    申请日：2011-12-05

    申请人： Kenneth A. Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

    发明人： Kenneth A. Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/0246 ,  G06F13/1668 ,  G06F2212/205 ,  Y02D10/14

    摘要： A translating memory module is disclosed including a printed circuit board, at least one memory integrated circuit coupled to the printed board, and at least one support chip coupled to the printed circuit board and coupled between the edge connector and the at least one memory integrated circuit. The at least one support chip includes a bi-directional translator to translate between a first memory communication protocol for the at least one memory integrated circuit and a second memory communication protocol for a memory channel differing from the first memory communication protocol. The second memory communication protocol to communicate data, address, and control signals over the memory channel bus to read and write data into the memory of the translating memory module.

    摘要翻译： 公开了一种翻译存储器模块，其包括印刷电路板，耦合到印刷电路板的至少一个存储器集成电路以及耦合到印刷电路板并耦合在边缘连接器和至少一个存储器集成电路之间的至少一个支撑芯片 。 所述至少一个支持芯片包括用于在用于所述至少一个存储器集成电路的第一存储器通信协议和用于不同于所述第一存储器通信协议的存储器通道的第二存储器通信协议之间转换的双向转换器。 第二存储器通信协议，用于通过存储器通道总线传送数据，地址和控制信号，以将数据读取和写入到转换存储器模块的存储器中。

    METHODS OF COMMUNICATING TO DIFFERENT TYPES OF MEMORY MODULES IN A MEMORY CHANNEL
    2.
    发明申请
    METHODS OF COMMUNICATING TO DIFFERENT TYPES OF MEMORY MODULES IN A MEMORY CHANNEL 有权
    在存储器通道中与不同类型的存储器模块通信的方法

    公开(公告)号：US20140075106A1

    公开(公告)日：2014-03-13

    申请号：US14016202

    申请日：2013-09-02

    申请人： Kenneth A. Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

    发明人： Kenneth A. Okin ,  George Moussa ,  Kumar Ganapathy ,  Vijay Karamcheti ,  Rajesh Parekh

    IPC分类号： G11C7/10

    CPC分类号： G11C7/1072 ,  G06F13/1694 ,  G11C5/04 ,  Y02D10/14

    摘要： A computer system is disclosed including a printed circuit board (PCB) including a plurality of traces, at least one processor mounted to the PCB to couple to some of the plurality of traces, a heterogeneous memory channel including a plurality of sockets coupled to a memory channel bus of the PCB, and a memory controller coupled between the at least one processor and the heterogeneous memory channel. The heterogeneous memory channel includes a plurality of sockets coupled to a memory channel bus of the PCB. The plurality of sockets are configured to receive a plurality of different types of memory modules. The memory controller may be a programmable heterogeneous memory controller to flexibly adapt to the memory channel bus to control access to each of the different types of memory modules in the heterogeneous memory channel.

    摘要翻译： 公开了一种计算机系统，其包括包括多个迹线的印刷电路板（PCB），至少一个处理器，其安装到PCB以耦合到多个迹线中的一些，异质存储器通道，包括耦合到存储器的多个插座 PCB的通道总线，以及耦合在所述至少一个处理器和所述异构存储器通道之间的存储器控​​制器。 异质存储器通道包括耦合到PCB的存储器通道总线的多个插座。 多个插槽被配置为接收多个不同类型的存储器模块。 存储器控制器可以是可编程异构存储器控制器，以灵活地适应存储器通道总线来控制对异质存储器通道中的每种不同类型的存储器模块的访问。

    WRITING TO ASYMMETRIC MEMORY
    3.
    发明申请
    WRITING TO ASYMMETRIC MEMORY 有权
    写入不对称记忆

    公开(公告)号：US20130007338A1

    公开(公告)日：2013-01-03

    申请号：US13608937

    申请日：2012-09-10

    申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    IPC分类号： G06F12/08

    CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

    摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

    摘要翻译： 存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。 计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性 写这个地址。 非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。

    Writing to asymmetric memory
    6.
    发明授权
    Writing to asymmetric memory 有权
    写入不对称记忆

    公开(公告)号：US07930513B2

    公开(公告)日：2011-04-19

    申请号：US11935281

    申请日：2007-11-05

    申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

    摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

    摘要翻译： 存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。 计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性 写这个地址。 非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。

    Writing to asymmetric memory
    10.
    发明授权
    Writing to asymmetric memory 有权
    写入不对称记忆

    公开(公告)号：US08266407B2

    公开(公告)日：2012-09-11

    申请号：US13053371

    申请日：2011-03-22

    申请人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    发明人： Vijay Karamcheti ,  Kenneth A. Okin ,  Kumar Ganapathy ,  Ashish Singhai ,  Rajesh Parekh

    IPC分类号： G06F12/00

    CPC分类号： G06F12/1009 ,  G06F3/0604 ,  G06F3/0628 ,  G06F3/0638 ,  G06F3/064 ,  G06F3/0646 ,  G06F3/0647 ,  G06F3/068 ,  G06F3/0685 ,  G06F9/5016 ,  G06F12/0207 ,  G06F12/0223 ,  G06F12/0292 ,  G06F12/08 ,  G06F12/10 ,  G06F12/121 ,  G06F12/1475 ,  G06F13/1657 ,  G06F13/1694 ,  G06F2212/205 ,  G06F2212/657 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/22

    摘要： A memory controller writes to a virtual address associated with data residing within an asymmetric memory component of main memory that is within a computer system and that has a symmetric memory component, while preserving proximate other data residing within the asymmetric memory component. The symmetric memory component within the main memory of the computer system is configured to enable random access write operations in which an address within a block of the symmetric memory component is written without affecting the availability of other addresses within the block of the symmetric memory component during the writing of that address. The asymmetric memory component is configured to enable block write operations in which writing to an address within a region of the asymmetric memory component affects the availability of other addresses within the region of the asymmetric memory component during the block write operations involving the address.

    摘要翻译： 存储器控制器写入与驻留在计算机系统内的主存储器的非对称存储器组件内的数据相关联的虚拟地址，并且具有对称存储器组件，同时保留驻留在非对称存储器组件内的邻近其他数据。 计算机系统的主存储器内的对称存储器组件被配置为实现随机存取写入操作，其中写入对称存储器组件的块内的地址而不影响对称存储器组件的块内的其他地址的可用性 写这个地址。 非对称存储器组件被配置为启用块写入操作，其中对非对称存储器组件的区域内的地址的写入在涉及地址的块写入操作期间影响非对称存储器组件的区域内的其他地址的可用性。