公开(公告)号：US06253323B1

公开(公告)日：2001-06-26

申请号：US08742981

申请日：1996-11-01

申请人： George W. Cox ,  David W. Aucsmith ,  Paul E. Onnen

发明人： George W. Cox ,  David W. Aucsmith ,  Paul E. Onnen

IPC分类号： H04L900

CPC分类号： H04L9/3247 ,  H04L9/3263

摘要： Briefly, in accordance with one embodiment of the invention, a method of using a digital signature includes: electronically referencing at least one plurality of electronic signals with a digital signature remotely stored from the plurality.

摘要翻译： 简而言之，根据本发明的一个实施例，一种使用数字签名的方法包括：用从多个远程存储的数字签名电子地引用至少一个多个电子信号。

公开(公告)号：US5634043A

公开(公告)日：1997-05-27

申请号：US295556

申请日：1994-08-25

申请人： Keith-Michael W. Self ,  Craig B. Peterson ,  James A. Sutton, II ,  John A. Urbanski ,  George W. Cox ,  Linda J. Rankin ,  David W. Archer ,  Shekhar Y. Borkar

发明人： Keith-Michael W. Self ,  Craig B. Peterson ,  James A. Sutton, II ,  John A. Urbanski ,  George W. Cox ,  Linda J. Rankin ,  David W. Archer ,  Shekhar Y. Borkar

IPC分类号： G06F15/173 ,  G06F1/10 ,  G06F1/12

CPC分类号： G06F15/17381

摘要： A computer system having at least a first microprocessor for processing information and a first memory coupled to the first microprocessor via a first point-to-point interface. The first point-to-point interface provides communication of signals between the first microprocessor and the first memory irrespective of the phase of the signals received by either the first microprocessor or the first memory. The first point-to-point interface includes a first point-to-point circuit in the microprocessor for receiving the signals from the first memory. The first point-to-point circuit and the microprocessor comprise a single integrated circuit in some implemented embodiments, providing ease of construction and design of systems having a variety of topologies. A second microprocessor may also be coupled to the first memory via a second point-to-point interface, the first microprocessor and the second microprocessor sharing the first memory for storage of information used by the first microprocessor and the second microprocessor. In this configuration, the first memory may include a duplicate cache store for the first microprocessor and the second microprocessor, in order to provide cache consistency for the two processors. The system may also include a first input-output device coupled via a second point-to-point interface to the first memory. A variety of topologies of processors, memories and input/output devices may be designed into "clusters" wherein each cluster communicated with one another for accesses, remote and local, for accessing input/output devices, and for maintaining cache consistency.

摘要翻译： 一种具有用于处理信息的至少第一微处理器和经由第一点对点接口耦合到第一微处理器的第一存储器的计算机系统。 第一点对点接口提供第一微处理器和第一存储器之间的信号通信，而与第一微处理器或第一存储器接收的信号的相位无关。 第一点对点接口包括用于接收来自第一存储器的信号的微处理器中的第一点对点电路。 第一点对点电路和微处理器在一些实现的实施例中包括单个集成电路，提供具有各种拓扑的系统的构造和设计的容易性。 第二微处理器还可以经由第二点对点接口耦合到第一存储器，第一微处理器和第二微处理器共享第一存储器以存储由第一微处理器和第二微处理器使用的信息。 在该配置中，第一存储器可以包括用于第一微处理器和第二微处理器的重复高速缓存存储器，以便为两个处理器提供高速缓存一致性。 该系统还可以包括经由第二点对点接口耦合到第一存储器的第一输入 - 输出设备。 处理器，存储器和输入/输出设备的各种拓扑可以被设计成“群集”，其中每个群集彼此通信用于访问远程和本地，用于访问输入/输出设备，以及用于维持高速缓存的一致性。

公开(公告)号：US4803622A

公开(公告)日：1989-02-07

申请号：US46633

申请日：1987-05-07

申请人： William L. Bain, Jr. ,  Robert C. Bedichek ,  George W. Cox ,  Gerhard Grassl ,  Craig B. Peterson ,  Justin R. Rattner ,  Gurbir Singh ,  Gurbir Singh ,  John L. Wipfli

发明人： William L. Bain, Jr. ,  Robert C. Bedichek ,  George W. Cox ,  Gerhard Grassl ,  Craig B. Peterson ,  Justin R. Rattner ,  Gurbir Singh ,  Gurbir Singh ,  John L. Wipfli

IPC分类号： G06F13/14 ,  G06F13/12 ,  G06F13/38 ,  G06F3/00

CPC分类号： G06F13/124

摘要： An I/O bus sequencer for providing a data path between an execution Unit (EU-10), a register file (14) and devices connected to a bus (28). A programmable logic array (PLA-18) stores a program which controls a service table (20). The service table includes a plurality of entries divided into fields. One of the fields when decoded instructs the PLA as to what kind of operation the bus sequencer is to perform. Line selection (priority) logic (22) connected to I/O request lines (30) and to the service table (20) determines which service table entry the PLA is to use. A bus interface connected to the I/O bus ports (26) and to the PLA (18) routes data between the I/O bus ports (26) and the register file (14), entries of which are controlled by use of register sets. The service table fields include register set descriptors for storing the status of register set buffers. The PLA decodes an ACCESS instruction to start an operation by loading the first register set descriptor, and then decodes sequential SUPPLY instructions to the entry. Each SUPPLY instruction loads an empty register set descriptor field to be used when the current register set descriptor field is exhausted.

摘要翻译： 一种用于在执行单元（EU-10），寄存器文件（14）和连接到总线（28）的设备之间提供数据路径的I / O总线定序器。 可编程逻辑阵列（PLA-18）存储控制服务表（20）的程序。 服务表包括分成字段的多个条目。 解码后的其中一个字段指示PLA对总线音序器执行什么样的操作。 连接到I / O请求线（30）和服务表（20）的线路选择（优先级）逻辑（22）确定PLA要使用的服务表条目。 连接到I / O总线端口（26）和PLA（18）的总线接口在I / O总线端口（26）和寄存器文件（14）之间路由数据，其条目通过使用寄存器 套。 服务表字段包括用于存储寄存器组缓冲器的状态的寄存器集描述符。 PLA通过加载第一个寄存器集描述符对ACCESS指令进行解码以开始操作，然后将顺序的SUPPLY指令解码到该条目。 每个SUPPLY指令加载当前寄存器集描述符字段耗尽时要使用的空寄存器集描述符字段。

公开(公告)号：US06165082A

公开(公告)日：2000-12-26

申请号：US233226

申请日：1999-01-19

申请人： George W. Cox

发明人： George W. Cox

IPC分类号： A63B57/00

CPC分类号： A63B57/0006 ,  A63B57/10

摘要： An above-ground device that semi-automatically tees golf balls at practice areas such as driving ranges, without requiring the golfer to bend down and tee each golf ball by hand following each practice shot. The device comprises a U-shaped conduit which is embedded in the foam rubber backing of the playing surface mat typically found at a teeing area of a driving range in such a way that the openings in the conduit directly communicate with two holes drilled though the playing surface mat so as to create a continuous pathway between the two holes through the conduit. A semi-rigid rod is inserted into the conduit of such length that when one end is flush with the playing surface mat the other end protrudes above the playing surface mat approximately to the height of a standard golf tee. The ends of the rod are flared to substantially the shape of a standard golf tee.

摘要翻译： 一种地面上的设备，可以在练习区域（例如驾驶范围）半自动地打高尔夫球，而不需要高尔夫球手在每次练习拍摄之后弯下身并用手打发每个高尔夫球。 该装置包括U形导管，其嵌入在通常在驱动范围的发球区域发现的游戏表面垫的泡沫橡胶背衬中，使得导管中的开口直接与通过演奏钻出的两个孔连通 以便通过导管在两个孔之间产生连续的路径。 半刚性杆被插入到导管中，其长度使得当一端与游戏表面垫平齐时，另一端突出到游戏表面垫的上方大约到标准高尔夫球座的高度。 杆的端部被扩张到基本上标准高尔夫球座的形状。

公开(公告)号：US4387427A

公开(公告)日：1983-06-07

申请号：US197655

申请日：1980-10-16

申请人： George W. Cox ,  Justin R. Rattner

发明人： George W. Cox ,  Justin R. Rattner

IPC分类号： G06F9/46 ,  G06F9/48 ,  G06F15/16

CPC分类号： G06F9/4881 ,  G06F9/468 ,  G06F9/546

摘要： A general-purpose, tightly-coupled multiprocessing system wherein processors share a common memory. A hardware-recognizable object (a process object) in memory stores access descriptors for controlling the type and extent of access to objects associated with a process, including one describing a buffered port. Another hardware-recognizable object (a processor object) associated with an executing process, stores access descriptors for controlling the type and extent of access to objects associated with a processor, including one describing a dispatching port. Task-dispatching functions are accomplished by hardware-controlled queuing mechanisms at the buffered ports and dispatching ports. These mechanisms allow different processes to communicate with each other and bind ready-to-run processes with available processors for execution.

摘要翻译： 一种通用的，紧密耦合的多处理系统，其中处理器共享公共存储器。 存储器中的硬件可识别对象（进程对象）存储访问描述符，用于控制对与进程相关联的对象的访问的类型和范围，包括描述缓冲端口的对象。 与执行过程相关联的另一硬件可识别对象（处理器对象）存储用于控制对与处理器相关联的对象的访问的类型和范围的访问描述符，包括描述调度端口的对象。 任务调度功能由缓冲端口和调度端口上的硬件控制的排队机制完成。 这些机制允许不同的进程相互通信，并且将可运行的进程与可用的处理器绑定以供执行。

公开(公告)号：US4315310A

公开(公告)日：1982-02-09

申请号：US79991

申请日：1979-09-28

申请人： John A. Bayliss ,  George W. Cox ,  Bert E. Forbes ,  Kevin C. Kahn

发明人： John A. Bayliss ,  George W. Cox ,  Bert E. Forbes ,  Kevin C. Kahn

IPC分类号： G06F12/02 ,  G06F13/12 ,  G06F13/42 ,  G06F15/16 ,  G06F15/177 ,  G06F3/00

CPC分类号： G06F12/0284 ,  G06F13/128 ,  G06F13/4208

摘要： An input/output processor architecture for providing an interface between peripheral subsystems and a generalized data processor. The interface processor enables data to be transferred between two address spaces (the generalized data processor address space and an external processor I/O address space) by mapping a portion of the I/O address space into a portion of the GDP address space. This mapping facility provides the peripheral subsystem with a "window" into the associated GDP subsystem. It accepts addresses within a certain subrange, or subranges, and translates them into references into one or more GDP data segments.A function-request facility provides a functional capability over certain objects within the GDP address space.The two facilities provide software on an external processor with a window into the address space of the GDP that enables the software, via the function request means, to send messages to and receive messages from the GDP and to manipulate an environment provided for the external processor within its address space.

摘要翻译： 一种用于在外围子系统和广义数据处理器之间提供接口的输入/输出处理器架构。 通过将I / O地址空间的一部分映射到GDP地址空间的一部分，接口处理器能够在两个地址空间（广义数据处理器地址空间和外部处理器I / O地址空间）之间传输数据。 该映射设施为外围子系统提供了一个“窗口”到相关的GDP子系统中。 它接受特定子范围内的地址或子范围，并将其转换为一个或多个GDP数据段的引用。 功能请求功能可以在GDP地址空间内的某些对象上提供功能。 这两个设施将外部处理器上的软件提供到GDP的地址空间中的窗口，使得软件能够通过功能请求装置向GDP发送消息并从其接收消息并且操纵为外部处理器提供的环境 在其地址空间内。

公开(公告)号：US4829425A

公开(公告)日：1989-05-09

申请号：US168635

申请日：1988-03-01

申请人： William L. Bain, Jr. ,  David G. Carson ,  George W. Cox ,  Robert C. Duzett ,  Brad W. Hosler ,  Scott A. Ogilvie ,  Craig B. Peterson ,  John L. Wipfli

发明人： William L. Bain, Jr. ,  David G. Carson ,  George W. Cox ,  Robert C. Duzett ,  Brad W. Hosler ,  Scott A. Ogilvie ,  Craig B. Peterson ,  John L. Wipfli

IPC分类号： G06F13/40

CPC分类号： G06F13/404

摘要： An I/O processor for controlling data transfer between a local bus and an I/O bus. An Execution Unit, an I/O bus sequencer, and a local bus sequencer are connected to a register file. The register file is uniformly addressed and each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer have read/write access to the register file. The register file is comprised of a plurality of register sets. The Execution Unit includes a programmed processor which is programmed to allocate the register sets among tasks running on the processor by passing register-set descriptors between the tasks in the form of messages. The local bus sequencer includes a packet-oriented multiprocessor bus, there being a variable number of bytes in each of the packets. The I/O sequencer includes logic for multibyte sequencing of data at a bus-dependent data rate between the I/O bus and the register file. Each of the tasks includes a task frame, each task frame including register-set pointers. The register-set pointers map between logical addresses used in the instructions of the tasks used to access the pointers and physical register-set addresses used to access the register. Programmed logic in each of the Execution Unit, the local bus sequencer, and the I/O bus sequencer dynamically allocate the register sets to the sending and destination tasks.

摘要翻译： 用于控制本地总线和I / O总线之间的数据传输的I / O处理器。 执行单元，I / O总线排序器和本地总线顺控程序连接到寄存器文件。 寄存器文件被均匀地寻址，执行单元，本地总线排序器和I / O总线排序器中的每一个具有对寄存器文件的读/写访问。 寄存器文件由多个寄存器组构成。 执行单元包括编程处理器，其被编程为通过在消息形式的任务之间传递寄存器集描述符来在处理器上运行的任务之间分配寄存器集。 本地总线定序器包括面向分组的多处理器总线，每个分组中存在可变数量的字节。 I / O定序器包括用于在I / O总线和寄存器文件之间以总线相关数据速率对数据进行多字节排序的逻辑。 每个任务包括任务帧，每个任务帧包括寄存器集指针。 寄存器集指针映射在用于访问指针的任务的指令中使用的逻辑地址和用于访问寄存器的物理寄存器集地址之间。 每个执行单元，本地总线排序器和I / O总线顺控程序中的程序逻辑动态地将寄存器组分配给发送和目标任务。

公开(公告)号：US4402046A

公开(公告)日：1983-08-30

申请号：US290135

申请日：1981-08-05

申请人： George W. Cox ,  Justin R. Rattner

发明人： George W. Cox ,  Justin R. Rattner

IPC分类号： G06F15/167 ,  G06F15/173 ,  G06F13/00

CPC分类号： G06F15/167 ,  G06F15/17337

摘要： A communication mechanism for use in a multi-processing system wherein several processors share a common memory. Each processor has associated with it a local communication segment, stored in memory. The local communication segment is for processor-specific communication. Another segment, the global communication segment, is common to all processors, and is for system-wide communication. Each communication segment has a field containing control flags. The flags are set by one processor and later inspected by the same or another processor. The inspecting processor is instructed to perform a number of functions specified by the state of the control flags. A count field and a lock field are provided in all communication segments to interlock access to the communication mechanism. A status field is provided in the local communication segments. Processors take the state of the status field into consideration when interpreting the control fla

摘要翻译： 一种用于多处理系统的通信机制，其中几个处理器共享公共存储器。 每个处理器与其相关联的本地通信段，存储在存储器中。 本地通信部分用于处理器特定的通信。 全球通信部分的另一个部分是所有处理器的共同之处，用于系统范围的通信。 每个通信段都有一个包含控制标志的字段。 这些标志由一个处理器设置，稍后由相同或另一个处理器检查。 指示检查处理器执行由控制标志的状态指定的多个功能。 在所有通信段中提供计数字段和锁定字段以互锁对通信机制的访问。 一个

公开(公告)号：US5896533A

公开(公告)日：1999-04-20

申请号：US498928

申请日：1995-07-06

申请人： Daniel Ramos ,  George W. Cox ,  Kevin Altis

发明人： Daniel Ramos ,  George W. Cox ,  Kevin Altis

IPC分类号： G06F9/46 ,  H04L29/06 ,  H04L29/08 ,  H04L29/12 ,  G06F15/163 ,  G06F9/00

CPC分类号： G06F9/543 ,  H04L29/06 ,  H04L67/02 ,  H04L67/2809 ,  H04L69/08 ,  H04L29/08846 ,  H04L29/12594 ,  H04L61/30 ,  H04L67/10 ,  H04L67/28

摘要： The method and apparatus of the present invention allows for all applications running on a computer which conform to the Object Linking and Embedding Application Programming Interface (OLE API) to automatically become capable of accessing World-Wide Web (WWW) files of arbitrary type. The standard OLE API is extended to utilize Uniform Resource Locators (URL), the WWW global naming convention,

摘要翻译： 本发明的方法和装置允许在符合对象链接和嵌入应用程序编程接口（OLE API）的计算机上运行的所有应用程序自动地能够访问任意类型的万维网（WWW）文件。 扩展标准的OLE API以使用统一资源定位符（URL），WWW全局命名约定，

公开(公告)号：US4325120A

公开(公告)日：1982-04-13

申请号：US971661

申请日：1978-12-21

申请人： Stephen R. Colley ,  George W. Cox ,  Justin R. Rattner ,  Roger C. Swanson

发明人： Stephen R. Colley ,  George W. Cox ,  Justin R. Rattner ,  Roger C. Swanson

IPC分类号： F02B75/02 ,  G06F9/44 ,  G06F9/46 ,  G06F9/48 ,  G06F13/00

CPC分类号： G06F9/4881 ,  G06F9/465 ,  G06F9/546 ,  F02B2075/027

摘要： A data processor architecture wherein the processors recognize two basic types of objects, an object being a representation of related information maintained in a contiguously-addresed set of memory locations. The first type of object contains ordinary data, such as characters, integers, reals, etc. The second type of object contains a list of access descriptors. Each access descriptor provides information for locating and defining the extent of access to an object associated with that access descriptor. The processors recognize complex objects that are combinations of objects of the basic types. One such complex object (a context) defines an environment for execution of objects accessible to a given instance of a procedural operation. The dispatching of tasks to the processors is accomplished by hardware-controlled queuing mechanisms (dispatching-port objects) which allow multiple sets of processors to serve multiple, but independent sets of tasks. Communication between asynchronous tasks or processes is accomplished by related hardware-controlled queuing mechanisms (buffered-port objects) which allow messages to move between internal processes or input/output processes without the need for interrupts. A mechanism is provided which allows the processors to communicate with each other. This mechanism is used to reawaken an idle processor to alert the processor to the fact that a ready-to-run process at a dispatching port needs execution.

摘要翻译： 一种数据处理器架构，其中处理器识别两种基本类型的对象，对象是维持在连续存储的存储器位置集合中的相关信息的表示。 第一种类型的对象包含普通数据，例如字符，整数，序列等。第二类对象包含访问描述符列表。 每个访问描述符提供用于定位和定义对与该访问描述符相关联的对象的访问范围的信息。 处理器识别作为基本类型的对象的组合的复杂对象。 一个这样的复杂对象（上下文）定义了用于执行程序操作的给定实例可访问的对象的环境。 通过硬件控制的排队机制（调度端口对象）来实现将任务分配到处理器，这些机制允许多组处理器提供多个但独立的任务集。 异步任务或进程之间的通信由相关硬件控制的排队机制（缓冲端口对象）完成，这些机制允许消息在内部进程或输入/输出进程之间移动，而不需要中断。 提供了允许处理器彼此通信的机制。 该机制用于重新唤醒空闲处理器以提醒处理器，即调度端口上的即时运行进程需要执行。