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公开(公告)号：US07600152B2
公开(公告)日：2009-10-06
申请号：US11926537
申请日：2007-10-29
申请人： Kevin J. Ash , David F. Mannenbach , Yu-Cheng Hsu
发明人： Kevin J. Ash , David F. Mannenbach , Yu-Cheng Hsu
IPC分类号： G06F11/00
CPC分类号： G06F12/0866 , G06F11/2089 , G06F2212/601
摘要： Disclosed are a storage controller, and a method of operating a storage controller, for interfacing between host systems and a storage devices system. The storage controller includes a first cluster including a first processor and a first cache, and a second cluster including a second processor and a second cache. The method comprises the step of directing data from the host systems through first and second data paths to the storage system. The first processor and cache are associated with the first data path, and the second processor and cache are associated with the second data path. Under one set of conditions, the controller enters a failover mode, wherein data directed to the first data path are routed to the second data path. Under another set of conditions, the controller deconfigures the first cache without entering the failover mode.
摘要翻译： 公开了存储控制器和操作存储控制器的方法，用于在主机系统和存储设备系统之间进行接口。 存储控制器包括包括第一处理器和第一高速缓存的第一群集，以及包括第二处理器和第二高速缓存的第二群集。 该方法包括将来自主机系统的数据通过第一和第二数据路径引导到存储系统的步骤。 第一处理器和高速缓存与第一数据路径相关联，并且第二处理器和高速缓存与第二数据路径相关联。 在一组条件下，控制器进入故障转移模式，其中指向第一数据路径的数据被路由到第二数据路径。 在另一组条件下，控制器解除配置第一个缓存而不进入故障切换模式。
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12.发明授权公开(公告)号：US07085907B2
公开(公告)日：2006-08-01
申请号：US10781467
申请日：2004-02-17
申请人： Kevin J. Ash , Richard H. Grossman , Joseph D. Ohrazda , Pablo A. Rodriguez , Tim S. Vande Zande
发明人： Kevin J. Ash , Richard H. Grossman , Joseph D. Ohrazda , Pablo A. Rodriguez , Tim S. Vande Zande
IPC分类号： G06F12/00
CPC分类号： G06F11/2089 , G06F3/0607 , G06F3/0632 , G06F3/0656 , G06F3/0689 , G06F12/0866
摘要： A data storage control unit is coupled to one or more host devices and to one or more physical storage units, the storage control unit configured as a plurality of clusters. Each cluster includes cache memory and often non-volatile storage (NVS). The storage control unit receives and processes write requests from the host devices and directs that data updates be temporarily stored in the cache in one cluster and copied to the NVS of the other cluster. The data updates are subsequently destaged to the logical ranks associated with each cluster. During an initial microcode load (IML) of the storage controller, space in the cache and NVS of each cluster is allocated to buffers with the remaining cache and NVS space being allocated to customer data. After an IML has been completed, the size of the buffers become fixed and no further buffer allocation may occur. Method, apparatus and program product are provided by which a data storage controller dynamically reconfigures NVS and cache memory in multiple clusters, particularly when it is desired to change the size of the NVS and cache of either or both clusters.
摘要翻译： 数据存储控制单元耦合到一个或多个主机设备和一个或多个物理存储单元，该存储控制单元被配置为多个集群。 每个集群包括高速缓存和通常的非易失性存储（NVS）。 存储控制单元接收并处理来自主机设备的写入请求，并指示数据更新临时存储在一个集群中的高速缓存中，并复制到另一个集群的NVS。 数据更新随后转移到与每个集群相关联的逻辑排名。 在存储控制器的初始微代码加载（IML）期间，每个集群的高速缓存和NVS中的空间被分配给缓冲区，其余的高速缓存和NVS空间被分配给客户数据。 在完成IML之后，缓冲区的大小变得固定，并且不会发生进一步的缓冲区分配。 提供了方法，装置和程序产品，数据存储控制器通过该产品动态地重新配置NVS和多个集群中的高速缓冲存储器，特别是当希望改变NVS和任一个或两个集群的高速缓存的大小时。
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公开(公告)号：US4891811A
公开(公告)日：1990-01-02
申请号：US14749
申请日：1987-02-13
CPC分类号： G11C29/42 , G11C29/02 , G11C29/10 , G11C29/18 , G06F11/076 , G06F11/1052
摘要： A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage work. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accesseed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart.
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公开(公告)号：US09021201B2
公开(公告)日：2015-04-28
申请号：US13352239
申请日：2012-01-17
CPC分类号： G06F12/0866 , G06F12/128
摘要： A determination is made of a track to demote from the first cache to the second cache, wherein the track in the first cache corresponds to a track in the storage system and is comprised of a plurality of sectors. In response to determining that the second cache includes a the stale version of the track being demoted from the first cache, a determination is made as to whether the stale version of the track includes track sectors not included in the track being demoted from the first cache. The sectors from the track demoted from the first cache are combined with sectors from the stale version of the track not included in the track being demoted from the first cache into a new version of the track. The new version of the track is written to the second cache.
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公开(公告)号：US08825973B2
公开(公告)日：2014-09-02
申请号：US13352201
申请日：2012-01-17
IPC分类号： G06F12/08
CPC分类号： G06F12/0802 , G06F12/0868
摘要： Provided are a computer program product, system, and method for processing a read operation for a target block of data. A read operation for the target block of data in target storage is received, wherein the target block of data is in an instant virtual copy relationship with a source block of data in source storage. It is determined that the target block of data in the target storage is not consistent with the source block of data in the source storage. The source block of data is retrieved. The data in the source block of data in the cache is synthesized to make the data appear to be retrieved from the target storage. The target block of data is marked as read from the source storage. In response to the read operation completing, the target block of data that was read from the source storage is demoted.
摘要翻译： 提供了一种用于处理目标数据块的读取操作的计算机程序产品，系统和方法。 接收目标存储器中目标数据块的读取操作，其中目标数据块与源存储器中的源数据块处于即时虚拟复制关系。 确定目标存储器中的目标数据块与源存储器中的数据源块不一致。 检索源数据块。 高速缓存中源数据块中的数据被合成，使数据看起来从目标存储器检索出来。 目标数据块被标记为从源存储器读取。 响应于读取操作完成，从源存储器读取的目标数据块被降级。
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16.发明授权公开(公告)号：US08812785B2
公开(公告)日：2014-08-19
申请号：US13113962
申请日：2011-05-23
IPC分类号： G06F12/00
CPC分类号： G06F12/0891 , G06F11/2089 , G06F11/2097 , G06F12/0866 , G06F2212/284 , G06F2212/286
摘要： Provided are a computer program product, system, and method for managing track discard requests to include in discard track messages. A backup copy of a track in a cache is maintained in the cache backup device. A track discard request is generated to discard tracks in the cache backup device removed from the cache. Track discard requests are queued in a discard track queue. In response to detecting that a predetermined number of track discard requests are queued in the discard track queue while processing in a discard multi-track mode, one discard multiple tracks message is sent indicating the tracks indicated in the queued predetermined number of track discard requests to the cache backup device instructing the cache backup device to discard the tracks indicated in the discard multiple tracks message. In response to determining a predetermined number of periods of inactivity while processing in the discard multi-track mode, processing the track discard requests is switched to a discard single track mode.
摘要翻译： 提供了一种用于管理跟踪丢弃请求以包括在丢弃轨道消息中的计算机程序产品，系统和方法。 高速缓存备份设备中维护缓存中磁道的备份副本。 生成跟踪丢弃请求，以丢弃从缓存中删除的缓存备份设备中的轨道。 跟踪丢弃请求在丢弃轨道队列中排队。 响应于在丢弃多轨道模式中检测到预定数量的轨道丢弃请求被排队在丢弃轨道队列中时，一个丢弃多个轨道消息被发送，指示在排队的预定数量的轨道丢弃请求中指示的轨道 缓存备份设备指示高速缓存备份设备丢弃丢弃多个轨道消息中指示的轨道。 响应于在丢弃多轨道模式中处理时确定预定数量的不活动周期，将轨道丢弃请求处理切换到丢弃单轨道模式。
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17.发明授权Managing unmodified tracks maintained in both a first cache and a second cache 有权管理在第一缓存和第二高速缓存中维护的未修改轨道公开(公告)号：US08700854B2
公开(公告)日：2014-04-15
申请号：US13476781
申请日：2012-05-21
IPC分类号： G06F12/00
CPC分类号： G06F12/0897 , G06F12/0871
摘要： Provided are a computer program product, system, and method for managing unmodified tracks maintained in both a first cache and a second cache. The first cache has unmodified tracks in the storage subject to Input/Output (I/O) requests. Unmodified tracks are demoted from the first cache to a second cache. An inclusive list indicates unmodified tracks maintained in both the first cache and a second cache. An exclusive list indicates unmodified tracks maintained in the second cache but not the first cache. The inclusive list and the exclusive list are used to determine whether to promote to the second cache an unmodified track demoted from the first cache.
摘要翻译： 提供了一种用于管理在第一高速缓存和第二高速缓存中保持的未修改轨道的计算机程序产品，系统和方法。 第一个缓存在存储器中具有未修改的轨道，需要输入/输出（I / O）请求。 未修改的轨道从第一缓存降级到第二缓存。 包含的列表指示在第一高速缓存和第二高速缓存中保持的未修改轨道。 排他列表指示在第二缓存中维护的未修改轨道，但不指示第一缓存。 包含列表和排他列表用于确定是否向第二缓存提升从第一高速缓存降级的未修改轨道。
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公开(公告)号：US20120303899A1
公开(公告)日：2012-11-29
申请号：US13113962
申请日：2011-05-23
IPC分类号： G06F12/08
CPC分类号： G06F12/0891 , G06F11/2089 , G06F11/2097 , G06F12/0866 , G06F2212/284 , G06F2212/286
摘要： Provided are a computer program product, system, and method for managing track discard requests to include in discard track messages. A backup copy of a track in a cache is maintained in the cache backup device. A track discard request is generated to discard tracks in the cache backup device removed from the cache. Track discard requests are queued in a discard track queue. In response to detecting that a predetermined number of track discard requests are queued in the discard track queue while processing in a discard multi-track mode, one discard multiple tracks message is sent indicating the tracks indicated in the queued predetermined number of track discard requests to the cache backup device instructing the cache backup device to discard the tracks indicated in the discard multiple tracks message. In response to determining a predetermined number of periods of inactivity while processing in the discard multi-track mode, processing the track discard requests is switched to a discard single track mode.
摘要翻译： 提供了一种用于管理跟踪丢弃请求以包括在丢弃轨道消息中的计算机程序产品，系统和方法。 高速缓存备份设备中维护缓存中磁道的备份副本。 生成跟踪丢弃请求，以丢弃从缓存中删除的缓存备份设备中的轨道。 跟踪丢弃请求在丢弃轨道队列中排队。 响应于在丢弃多轨道模式中检测到预定数量的轨道丢弃请求被排队在丢弃轨道队列中时，一个丢弃多个轨道消息被发送，指示在排队的预定数量的轨道丢弃请求中指示的轨道 缓存备份设备指示高速缓存备份设备丢弃丢弃多个轨道消息中指示的轨道。 响应于在丢弃多轨道模式中处理时确定预定数量的不活动周期，将轨道丢弃请求处理切换到丢弃单轨道模式。
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公开(公告)号：US20120151143A1
公开(公告)日：2012-06-14
申请号：US13399579
申请日：2012-02-17
申请人： Kevin J. Ash , Richard A. Ripberger
发明人： Kevin J. Ash , Richard A. Ripberger
IPC分类号： G06F12/08
CPC分类号： G06F12/0866 , G06F11/0727 , G06F11/076 , G06F2212/222
摘要： A technique for limiting an amount of write data stored in a cache memory includes determining a usable region of a non-volatile storage (NVS), determining an amount of write data in a current write request for the cache memory, and determining a failure boundary associated with the current write request. A count of the write data associated with the failure boundary is maintained. The current write request for the cache memory is rejected when a sum of the count of the write data associated with the failure boundary and the write data in the current write request exceeds a determined percentage of the usable region of the NVS.
摘要翻译： 用于限制存储在高速缓冲存储器中的写入数据量的技术包括：确定非易失性存储器（NVS）的可用区域，确定当前高速缓存存储器的写入请求中的写入数据量，以及确定故障边界 与当前写入请求相关联。 保持与故障边界相关联的写入数据的计数。 当与故障边界相关联的写入数据的计数与当前写入请求中的写入数据的总和超过NVS的可用区域的确定百分比时，缓存存储器的当前写入请求被拒绝。
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公开(公告)号：US20110191534A1
公开(公告)日：2011-08-04
申请号：US12697385
申请日：2010-02-01
申请人： Kevin J. Ash , Lokesh M. Gupta
发明人： Kevin J. Ash , Lokesh M. Gupta
CPC分类号： G06F12/0868 , G06F12/0804 , G06F2212/261 , G06F2212/502
摘要： Method, system, and computer program product embodiments for facilitating data transfer from a write cache and NVS via a device adapter to a pool of storage devices by a processor or processors are provided. The processor(s) adaptively varies the destage rate based on the current occupancy of the NVS for a particular storage device and stage activity related to that storage device. The stage activity includes one or more of the storage device stage activity, device adapter stage activity, device adapter utilized bandwidth and the read/write speed of the storage device. These factors are generally associated with read response time in the event of a cache miss and not ordinarily associated with dynamic management of the destage rate. This combination maintains the desired overall occupancy of the NVS while improving response time performance.
摘要翻译： 提供了方法，系统和计算机程序产品实施例，用于促进通过处理器或处理器从写入高速缓存和NVS经由设备适配器到存储设备池的数据传输。 处理器根据特定存储设备的NVS的当前占用率和与该存储设备相关的阶段活动自适应地改变流水率。 舞台活动包括存储设备舞台活动，设备适配器舞台活动，设备适配器利用带宽和存储设备的读/写速度中的一个或多个。 这些因素通常与高速缓存未命中的读取响应时间相关联，并且通常不与流动速率的动态管理相关联。 这种组合在提高响应时间性能的同时保持NVS的期望总体占用。
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