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    POPULATING A FIRST STRIDE OF TRACKS FROM A FIRST CACHE TO WRITE TO A SECOND STRIDE IN A SECOND CACHE
    2.
    发明申请
    POPULATING A FIRST STRIDE OF TRACKS FROM A FIRST CACHE TO WRITE TO A SECOND STRIDE IN A SECOND CACHE 有权
    将第一个缓存的第一个路径从第一个缓存中写入第二个缓冲区

    公开(公告)号：US20130185478A1

    公开(公告)日：2013-07-18

    申请号：US13464668

    申请日：2012-05-04

    申请人： Kevin J. Ash ,  Michael T. Benhase ,  Lokesh M. Gupta ,  Matthew J. Kalos ,  Karl A. Nielsen

    发明人： Kevin J. Ash ,  Michael T. Benhase ,  Lokesh M. Gupta ,  Matthew J. Kalos ,  Karl A. Nielsen

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0868 ,  G06F12/0804 ,  G06F12/0897 ,  G06F12/128 ,  G06F2212/262 ,  G06F2212/312 ,  G06F2212/462

    摘要： Provided are a computer program product, system, and method for managing data in a cache system comprising a first cache, a second cache, and a storage system. A determination is made of tracks stored in the storage system to demote from the first cache. A first stride is formed including the determined tracks to demote. A determination is made of a second stride in the second cache in which to include the tracks in the first stride. The tracks from the first stride are added to the second stride in the second cache. A determination is made of tracks in strides in the second cache to demote from the second cache. The determined tracks to demote from the second cache are demoted.

    摘要翻译： 提供了一种用于管理包括第一高速缓存，第二高速缓存和存储系统的高速缓存系统中的数据的计算机程序产品，系统和方法。 确定存储在存储系统中的轨道以从第一高速缓存降级。 形成第一步，包括确定的轨道降级。 确定在第二高速缓存中的第二步，其中包括在第一步中的轨道。 来自第一步的轨道被添加到第二缓存中的第二步。 确定第二高速缓存中的步幅中的轨迹以从第二高速缓存降级。 确定的从第二个缓存降级的轨迹将被降级。

    Nonvolatile storage thresholding
    4.
    发明授权
    Nonvolatile storage thresholding 有权
    非易失性存储阈值

    公开(公告)号：US08140811B2

    公开(公告)日：2012-03-20

    申请号：US12489107

    申请日：2009-06-22

    申请人： Kevin J. Ash ,  Lokesh M. Gupta ,  Matthew J. Kalos ,  Alfred E. Sanchez ,  Kenneth W. Todd

    发明人： Kevin J. Ash ,  Lokesh M. Gupta ,  Matthew J. Kalos ,  Alfred E. Sanchez ,  Kenneth W. Todd

    IPC分类号： G06F12/08 ,  G06F13/00

    CPC分类号： G06F12/0804 ,  G06F12/0866 ,  G06F2212/214

    摘要： Embodiments for facilitating data transfer between a nonvolatile storage (NVS) write cache and a pool of target storage devices are provided. Each target storage device in the pool of target storage devices is determined as one of a hard disk drive (HDD) and a solid-state drive (SSD) device, and classified into one of a SSD rank group and a HDD rank group. If no data is received in the NVS write cache for a predetermined time to be written to a target storage device classified in the SSD rank group, a threshold of available space in the NVS write cache is set to allocate at least a majority of the available space to the HDD rank group. Upon receipt of a write request for the SSD rank group, the threshold of the available space is reduced to allocate a greater portion of the available space to the SSD rank group.

    摘要翻译： 提供了用于促进非易失性存储（NVS）写入高速缓存和目标存储设备池之间的数据传输的实施例。 目标存储设备池中的每个目标存储设备被确定为硬盘驱动器（HDD）和固态驱动器（SSD）设备之一，并且被分类为SSD等级组和HDD等级组之一。 如果在NVS写入高速缓存中没有数据被接收到预定时间被写入到SSD等级组中的目标存储设备上，则NVS写入高速缓存中的可用空间阈值被设置为分配至少大部分可用的 空间到HDD排名组。 在接收到SSD等级组的写入请求时，可用空间的阈值被减小以将更大部分的可用空间分配给SSD等级组。

    Techniques For Managing Data In A Write Cache Of A Storage Controller
    5.
    发明申请
    Techniques For Managing Data In A Write Cache Of A Storage Controller 失效
    用于在存储控制器的写缓存中管理数据的技术

    公开(公告)号：US20110016271A1

    公开(公告)日：2011-01-20

    申请号：US12504222

    申请日：2009-07-16

    申请人： Kevin J. Ash ,  Richard A. Ripberger

    发明人： Kevin J. Ash ,  Richard A. Ripberger

    IPC分类号： G06F12/08 ,  G06F12/00

    CPC分类号： G06F12/0866 ,  G06F11/0727 ,  G06F11/076 ,  G06F2212/222

    摘要： A technique for limiting an amount of write data stored in a cache memory includes determining a usable region of a non-volatile storage (NVS), determining an amount of write data in a current write request for the cache memory, and determining a failure boundary associated with the current write request. A count of the write data associated with the failure boundary is maintained. The current write request for the cache memory is rejected when a sum of the count of the write data associated with the failure boundary and the write data in the current write request exceeds a determined percentage of the usable region of the NVS.

    摘要翻译： 用于限制存储在高速缓冲存储器中的写入数据量的技术包括：确定非易失性存储器（NVS）的可用区域，确定当前高速缓存存储器的写入请求中的写入数据量，以及确定故障边界 与当前写入请求相关联。 保持与故障边界相关联的写入数据的计数。 当与故障边界相关联的写入数据的计数与当前写入请求中的写入数据的总和超过NVS的可用区域的确定百分比时，缓存存储器的当前写入请求被拒绝。

    Configuring cache memory from a storage controller
    6.
    发明授权
    Configuring cache memory from a storage controller 失效
    从存储控制器配置缓存内存

    公开(公告)号：US07600152B2

    公开(公告)日：2009-10-06

    申请号：US11926537

    申请日：2007-10-29

    申请人： Kevin J. Ash ,  David F. Mannenbach ,  Yu-Cheng Hsu

    发明人： Kevin J. Ash ,  David F. Mannenbach ,  Yu-Cheng Hsu

    IPC分类号： G06F11/00

    CPC分类号： G06F12/0866 ,  G06F11/2089 ,  G06F2212/601

    摘要： Disclosed are a storage controller, and a method of operating a storage controller, for interfacing between host systems and a storage devices system. The storage controller includes a first cluster including a first processor and a first cache, and a second cluster including a second processor and a second cache. The method comprises the step of directing data from the host systems through first and second data paths to the storage system. The first processor and cache are associated with the first data path, and the second processor and cache are associated with the second data path. Under one set of conditions, the controller enters a failover mode, wherein data directed to the first data path are routed to the second data path. Under another set of conditions, the controller deconfigures the first cache without entering the failover mode.

    摘要翻译： 公开了存储控制器和操作存储控制器的方法，用于在主机系统和存储设备系统之间进行接口。 存储控制器包括包括第一处理器和第一高速缓存的第一群集，以及包括第二处理器和第二高速缓存的第二群集。 该方法包括将来自主机系统的数据通过第一和第二数据路径引导到存储系统的步骤。 第一处理器和高速缓存与第一数据路径相关联，并且第二处理器和高速缓存与第二数据路径相关联。 在一组条件下，控制器进入故障转移模式，其中指向第一数据路径的数据被路由到第二数据路径。 在另一组条件下，控制器解除配置第一个缓存而不进入故障切换模式。

    Dynamic reconfiguration of memory in a multi-cluster storage control unit
    7.
    发明授权
    Dynamic reconfiguration of memory in a multi-cluster storage control unit 失效
    多集群存储控制单元中的内存动态重新配置

    公开(公告)号：US07085907B2

    公开(公告)日：2006-08-01

    申请号：US10781467

    申请日：2004-02-17

    申请人： Kevin J. Ash ,  Richard H. Grossman ,  Joseph D. Ohrazda ,  Pablo A. Rodriguez ,  Tim S. Vande Zande

    发明人： Kevin J. Ash ,  Richard H. Grossman ,  Joseph D. Ohrazda ,  Pablo A. Rodriguez ,  Tim S. Vande Zande

    IPC分类号： G06F12/00

    CPC分类号： G06F11/2089 ,  G06F3/0607 ,  G06F3/0632 ,  G06F3/0656 ,  G06F3/0689 ,  G06F12/0866

    摘要： A data storage control unit is coupled to one or more host devices and to one or more physical storage units, the storage control unit configured as a plurality of clusters. Each cluster includes cache memory and often non-volatile storage (NVS). The storage control unit receives and processes write requests from the host devices and directs that data updates be temporarily stored in the cache in one cluster and copied to the NVS of the other cluster. The data updates are subsequently destaged to the logical ranks associated with each cluster. During an initial microcode load (IML) of the storage controller, space in the cache and NVS of each cluster is allocated to buffers with the remaining cache and NVS space being allocated to customer data. After an IML has been completed, the size of the buffers become fixed and no further buffer allocation may occur. Method, apparatus and program product are provided by which a data storage controller dynamically reconfigures NVS and cache memory in multiple clusters, particularly when it is desired to change the size of the NVS and cache of either or both clusters.

    摘要翻译： 数据存储控制单元耦合到一个或多个主机设备和一个或多个物理存储单元，该存储控制单元被配置为多个集群。 每个集群包括高速缓存和通常的非易失性存储（NVS）。 存储控制单元接收并处理来自主机设备的写入请求，并指示数据更新临时存储在一个集群中的高速缓存中，并复制到另一个集群的NVS。 数据更新随后转移到与每个集群相关联的逻辑排名。 在存储控制器的初始微代码加载（IML）期间，每个集群的高速缓存和NVS中的空间被分配给缓冲区，其余的高速缓存和NVS空间被分配给客户数据。 在完成IML之后，缓冲区的大小变得固定，并且不会发生进一步的缓冲区分配。 提供了方法，装置和程序产品，数据存储控制器通过该产品动态地重新配置NVS和多个集群中的高速缓冲存储器，特别是当希望改变NVS和任一个或两个集群的高速缓存的大小时。

    Efficient address test for large memories
    8.
    发明授权
    Efficient address test for large memories 失效
    高效地址测试用于大容量存储器

    公开(公告)号：US4891811A

    公开(公告)日：1990-01-02

    申请号：US14749

    申请日：1987-02-13

    申请人： Kevin J. Ash ,  Jack H. Derenburger ,  Raymond L. Parsons

    发明人： Kevin J. Ash ,  Jack H. Derenburger ,  Raymond L. Parsons

    IPC分类号： G01R31/28 ,  G06F11/00 ,  G06F11/10 ,  G11C29/02 ,  G11C29/10 ,  G11C29/18 ,  G11C29/42

    CPC分类号： G11C29/42 ,  G11C29/02 ,  G11C29/10 ,  G11C29/18 ,  G06F11/076 ,  G06F11/1052

    摘要： A memory may contain a large number of bytes of data perhaps as many as 256 megabytes in a typical large memory structure. An error correcting code algorithm may be used to identify failing memory modules in a memory system. In a particular embodiment, a number of spares may be provided on each memory card allowing a predetermined number of defective array modules to be replaced in a storage work. With double bit correction provided by the error correcting code logic, a number of bits can be corrected on a card or a larger number of bits can be corrected on a card pair, where the larger number of bits is somewhat less than double the number of bits which can be corrected on a single card. The address test in accordance with the present invention then produces a pattern that will create a difference greater than that larger number of bits between the data stored in a storage location under test and any address that could be accesseed by an address line failure. The method according to the present invention predicts the effect of an address line failure external to the array modules and internal to a card pair and then tests to see if a failure has occurred. The address test does not declare an address failure until a predetermined number of bit failures on a card is found. The test is valid for single and multiple address line failures. Since only one address bit is changed for each path through the test other failing address lines will not be detected until the path with those failing address bits are tested. Thus, even with multiple address line failure the two addresses that are stored to and fetched from are the only one address bit apart.

    Demoting partial tracks from a first cache to a second cache
    9.
    发明授权
    Demoting partial tracks from a first cache to a second cache 有权

    公开(公告)号：US09021201B2

    公开(公告)日：2015-04-28

    申请号：US13352239

    申请日：2012-01-17

    申请人： Kevin J. Ash ,  Michael T. Benhase ,  Lokesh M. Gupta

    发明人： Kevin J. Ash ,  Michael T. Benhase ,  Lokesh M. Gupta

    IPC分类号： G06F12/00 ,  G06F13/00 ,  G06F13/28 ,  G06F12/08 ,  G06F12/12

    CPC分类号： G06F12/0866 ,  G06F12/128

    摘要： A determination is made of a track to demote from the first cache to the second cache, wherein the track in the first cache corresponds to a track in the storage system and is comprised of a plurality of sectors. In response to determining that the second cache includes a the stale version of the track being demoted from the first cache, a determination is made as to whether the stale version of the track includes track sectors not included in the track being demoted from the first cache. The sectors from the track demoted from the first cache are combined with sectors from the stale version of the track not included in the track being demoted from the first cache into a new version of the track. The new version of the track is written to the second cache.

    Caching source blocks of data for target blocks of data
    10.
    发明授权
    Caching source blocks of data for target blocks of data 有权
    缓存目标数据块的数据源块

    公开(公告)号：US08825973B2

    公开(公告)日：2014-09-02

    申请号：US13352201

    申请日：2012-01-17

    申请人： Kevin J. Ash ,  Michael T. Benhase ,  Lokesh M. Gupta ,  Matthew J. Kalos

    发明人： Kevin J. Ash ,  Michael T. Benhase ,  Lokesh M. Gupta ,  Matthew J. Kalos

    IPC分类号： G06F12/08

    CPC分类号： G06F12/0802 ,  G06F12/0868

    摘要： Provided are a computer program product, system, and method for processing a read operation for a target block of data. A read operation for the target block of data in target storage is received, wherein the target block of data is in an instant virtual copy relationship with a source block of data in source storage. It is determined that the target block of data in the target storage is not consistent with the source block of data in the source storage. The source block of data is retrieved. The data in the source block of data in the cache is synthesized to make the data appear to be retrieved from the target storage. The target block of data is marked as read from the source storage. In response to the read operation completing, the target block of data that was read from the source storage is demoted.

    摘要翻译： 提供了一种用于处理目标数据块的读取操作的计算机程序产品，系统和方法。 接收目标存储器中目标数据块的读取操作，其中目标数据块与源存储器中的源数据块处于即时虚拟复制关系。 确定目标存储器中的目标数据块与源存储器中的数据源块不一致。 检索源数据块。 高速缓存中源数据块中的数据被合成，使数据看起来从目标存储器检索出来。 目标数据块被标记为从源存储器读取。 响应于读取操作完成，从源存储器读取的目标数据块被降级。