公开(公告)号：US5787134A

公开(公告)日：1998-07-28

申请号：US324747

申请日：1994-10-18

申请人： Janos Kovacs

发明人： Janos Kovacs

IPC分类号： H03L7/093 ,  H03D3/24

CPC分类号： H03L7/093 ,  H03L2207/04

摘要： A switched capacitance phase locked loop (PLL) system includes a filter circuit having a scaling channel for scaling the phase error; an integrating channel for integrating the phase error; and a summing device for combining the scaled phase error and the integrated phase error; a voltage controlled oscillator (VCO) responsive to the summing device produces an output; the VCO's gain is proportional to its output clock frequency; the integrating channel includes a switched capacitance integrating circuit for controlling the gain of the integrating channel proportional to the output clock frequency of the VCO and maintaining constant the ratio of, and scaling the product of, the unity gain frequency and the zero frequency of the phase locked loop to keep constant the damping factor and to scale the natural frequency of the phase locked loop with the output clock frequency of the VCO, respectively.

摘要翻译： 开关电容锁相环（PLL）系统包括具有用于缩放相位误差的缩放通道的滤波器电路; 用于整合相位误差的积分通道; 以及用于组合缩放相位误差和积分相位误差的求和装置; 响应于求和装置的压控振荡器（VCO）产生输出; VCO的增益与其输出时钟频率成比例; 积分通道包括开关电容积分电路，用于控制与VCO的输出时钟频率成比例的积分通道的增益，并保持恒定的单位增益频率和相位的零频率的比值和比例 锁定环路保持阻尼因子的不变，并分别用VCO的输出时钟频率来缩放锁相环的固有频率。

公开(公告)号：US5525986A

公开(公告)日：1996-06-11

申请号：US317383

申请日：1994-10-04

申请人： Janos Kovacs ,  Steven R. Robinson ,  Wyn Palmer

发明人： Janos Kovacs ,  Steven R. Robinson ,  Wyn Palmer

IPC分类号： H03M1/78

CPC分类号： H03M1/785

摘要： An intrinsic R2R resistance ladder digital to analog converter (DAC) includes a plurality of matched semiconductor ladder switches, one in each of the R and 2R legs of the R2R ladder. The ON resistance of each semiconductor switch being matched to constitute the resistance ladder of the DAC; the ladder switches being operated in response to the digital signal input to the DAC; a reference circuit including a reference semiconductor switch matched with the ladder switches responsive to a reference current to generate a reference voltage; and a voltage follower circuit for monitoring the reference voltage and adjusting the current through the ladder switches to match the voltage at each ladder switch with the reference voltage for precisely fixing the DAC analog output current as a proportion of the reference current in dependence upon the operation of the ladder switches by the digital input signal.

摘要翻译： 固有的R2R电阻梯形数模转换器（DAC）包括多个匹配的半导体梯形开关，R2R梯子的R和2R脚中的每一个都有一个。 每个半导体开关的导通电阻匹配构成DAC的电阻梯形图; 梯形开关响应于输入到DAC的数字信号而被操作; 参考电路，包括响应于参考电流与梯形开关匹配的参考半导体开关以产生参考电压; 以及电压跟随器电路，用于监视参考电压并调节通过梯形开关的电流以将每个梯形开关的电压与参考电压相匹配，以根据操作精确地将DAC模拟输出电流固定为参考电流的一部分 的梯形图由数字输入信号切换。

公开(公告)号：US20080123658A1

公开(公告)日：2008-05-29

申请号：US11604842

申请日：2006-11-28

申请人： Simo Hyytia ,  Janos Kovacs ,  Zoltan Kis ,  Krisztian Litkey

发明人： Simo Hyytia ,  Janos Kovacs ,  Zoltan Kis ,  Krisztian Litkey

IPC分类号： H04L12/56

CPC分类号： H04L69/18 ,  H04L45/00 ,  H04L67/24 ,  H04L67/303 ,  H04W4/12

摘要： The invention relates to a method in which a message is received to a communication server from a node. The communication server obtains user information with recipient information in the message. The user information comprises user entity state and user entity protocol information. A first protocol is determined to become a preferred protocol based on the user entity protocol information. The delivery of said message is attempted with a delivery mechanism of the preferred protocol. A second protocol is determined to become the preferred protocol with said user entity protocol information upon a failure to deliver said message with said first protocol. The attempting of the delivery of said message is repeated with a delivery mechanism of the preferred protocol.

摘要翻译： 本发明涉及一种从节点向通信服务器接收消息的方法。 通信服务器在消息中获取具有收件人信息的用户信息。 用户信息包括用户实体状态和用户实体协议信息。 基于用户实体协议信息确定第一协议成为优选协议。 用优选协议的传送机制尝试传送所述消息。 在第二协议被确定为成为具有所述用户实体协议信息的优先协议时，无法使用所述第一协议传递所述消息。 用优选协议的传送机制重复传递所述消息的尝试。

公开(公告)号：US5995543A

公开(公告)日：1999-11-30

申请号：US885978

申请日：1997-06-30

申请人： Janos Kovacs ,  Jack Kenney

发明人： Janos Kovacs ,  Jack Kenney

IPC分类号： G11B20/10 ,  H04L25/03 ,  H03D1/00

CPC分类号： G11B20/10046 ,  G11B20/10009 ,  H04L25/03203

摘要： A constrained fixed delay tree search receiver for an MTR=2 encoded communication channel includes a filter circuit responsive to a received signal for producing a channel impulse response including a plurality of filtered samples with at least one of the post cursor filter samples forced to zero; a feedback equalizer circuit responsive to the channel symbol identified at the output of the receiver and the filtered samples for producing corresponding truncated samples comprised of linear combinations of coefficients characterizing the channel and channel symbols constrained by the MTR=2 code; and a detector including a discrete time filter responsive to the truncated samples for generating a set of signals defining a multi-segment boundary which divides the combination of the set of signals into two groups; a comparator circuit responsive to the discrete time filter for determining to which of the groups the combination of the set of signals belongs, and a logic circuit, responsive to the comparator circuit, for determining the value of a channel symbol as a function of the group in which the set of symbols belongs.

摘要翻译： 用于MTR = 2编码通信信道的约束固定延迟树搜索接收机包括响应于接收信号的滤波器电路，用于产生包括多个经滤波样本的信道脉冲响应，其中至少一个后光标滤波器样本被强制为零; 响应于在接收机的输出处识别的信道符号的反馈均衡器电路和用于产生由表征由信道和由MTR = 2码限制的信道符号的系数的线性组合组成的相应截断样本的滤波样本; 以及检测器，其包括响应于所述截断样本的离散时间滤波器，用于生成限定将所述一组信号的组合分成两组的多段边界的一组信号; 响应于离散时间滤波器的比较器电路，用于确定属于该组信号的组合的组中的哪个组以及响应于比较器电路的用于确定作为组的函数的信道符号的值的逻辑电路 其中符号集合属于其中。

公开(公告)号：US5373400A

公开(公告)日：1994-12-13

申请号：US161047

申请日：1993-12-01

申请人： Janos Kovacs

发明人： Janos Kovacs

IPC分类号： G11B20/10 ,  H03K5/08 ,  H04L25/06 ,  G11B5/09 ,  H03D1/00 ,  H03K5/153 ,  H04L27/06

CPC分类号： H03K5/086 ,  G11B20/10009 ,  H04L25/063

摘要： A maximum likelihood detector for a continuous time disk drive read channel includes a dynamic threshold updating circuit for a maximum likelihood detector using both positive and negative comparators for detecting the positive and negative peaks of an input signal; this includes comparing the input signal with at least one present dynamic threshold to produce positive and negative binary gating signals; a control circuit responsive to the binary gating signals, to the input signal, and to the peak detector circuit which identifies qualified input signal peaks; and a threshold update circuit responsive to the identification of qualified input signal peaks, which adjusts the present dynamic threshold by the difference between the input signal and the present dynamic threshold to obtain the next dynamic threshold.

摘要翻译： 用于连续时间盘驱动器读取通道的最大似然检测器包括用于最大似然检测器的动态阈值更新电路，其使用正和负比较器两者来检测输入信号的正峰值和负峰值; 这包括将输入信号与至少一个当前动态阈值进行比较以产生正和负二进制选通信号; 响应于二进门选通信号的控制电路，输入信号，以及峰值检测器电路，其识别合格的输入信号峰值; 以及响应于合格输入信号峰值的识别的阈值更新电路，其通过输入信号和当前动态阈值之间的差来调整当前动态阈值以获得下一个动态阈值。

公开(公告)号：US08311046B2

公开(公告)日：2012-11-13

申请号：US11604842

申请日：2006-11-28

申请人： Simo Hyytia ,  Janos Kovacs ,  Zoltan Kis ,  Krisztian Litkey

发明人： Simo Hyytia ,  Janos Kovacs ,  Zoltan Kis ,  Krisztian Litkey

IPC分类号： H04L12/28

CPC分类号： H04L69/18 ,  H04L45/00 ,  H04L67/24 ,  H04L67/303 ,  H04W4/12

摘要： The invention relates to a method in which a message is received to a communication server from a node. The communication server obtains user information with recipient information in the message. The user information comprises user entity state and user entity protocol information. A first protocol is determined to become a preferred protocol based on the user entity protocol information. The delivery of said message is attempted with a delivery mechanism of the preferred protocol. A second protocol is determined to become the preferred protocol with said user entity protocol information upon a failure to deliver said message with said first protocol. The attempting of the delivery of said message is repeated with a delivery mechanism of the preferred protocol.

摘要翻译： 本发明涉及一种从节点向通信服务器接收消息的方法。 通信服务器在消息中获取具有收件人信息的用户信息。 用户信息包括用户实体状态和用户实体协议信息。 基于用户实体协议信息确定第一协议成为优选协议。 用优选协议的传送机制尝试传送所述消息。 在第二协议被确定为成为具有所述用户实体协议信息的优先协议时，无法使用所述第一协议传递所述消息。 用优选协议的传送机制重复传递所述消息的尝试。

公开(公告)号：US5768320A

公开(公告)日：1998-06-16

申请号：US523648

申请日：1995-09-05

申请人： Janos Kovacs ,  Ronald Kroesen ,  Philip Quinlan

发明人： Janos Kovacs ,  Ronald Kroesen ,  Philip Quinlan

IPC分类号： G11B5/09 ,  G11B20/10

CPC分类号： G11B20/10175 ,  G11B20/10009 ,  G11B5/09

摘要： A read system for implementing PR4 and higher order PRML signals includes: a continuous time programmable filter, for receiving a read signal representative of a binary signal from a storage medium and for shaping the read signal into a PR4 shaped read signal; an analog finite impulse response (AFIR) filter, responsive to the continuous time programmable filter, for sampling and forming the PR4 shaped read signal into a PR4 shaped multilevel read signal; an analog to digital converter, responsive to the AFIR filter, for converting the PR4 shaped multilevel read signal from analog to digital; a data sequence filter, responsive to the analog to digital converter, for transforming the PR4 shaped multilevel digital read signal to a predetermined order PRML signal; and a Viterbi detector, responsive to the data sequence filter, for detecting the binary signal from the predetermined order PRML signal.

摘要翻译： 用于实现PR4和更高阶PRML信号的读取系统包括：连续时间可编程滤波器，用于从存储介质接收表示二进制信号的读取信号，并将读取信号整形为PR4形读取信号; 响应于连续时间可编程滤波器的模拟有限脉冲响应（AFIR）滤波器，用于将PR4形读取信号采样并形成为PR4形多电平读信号; 响应于AFIR滤波器的模数转换器，用于将PR4形多级读取信号从模拟转换成数字; 响应于所述模数转换器的数据序列滤波器，用于将所述PR4形多级数字读信号转换成预定顺序PRML信号; 以及响应于数据序列滤波器的维特比检测器，用于检测来自预定顺序PRML信号的二进制信号。

公开(公告)号：US5671252A

公开(公告)日：1997-09-23

申请号：US310050

申请日：1994-09-21

申请人： Janos Kovacs ,  Scott C. Munroe

发明人： Janos Kovacs ,  Scott C. Munroe

IPC分类号： H04L25/03 ,  H04L25/497 ,  H04L27/06

CPC分类号： H04L25/03133 ,  H04L25/497

摘要： A data receiving and processing channel including analog signal processing circuitry operable for receiving data in the form of an input analog signal, and modifying the input signal in accordance with selected parameters so as to generate a modified analog input signal. According to one embodiment, there is provided a charge domain signal equalizer which initially transforms the modified analog input signal into a corresponding analog charge domain signal, the equalizer performing waveform shaping of the analog charge domain signal in accordance with a predetermined signal response template; a charge domain analog-to-digital converter operable for converting the analog charge domain signal into a corresponding digital signal; and a digital signal processor operable for recovering a digital bit stream from the digital signal which is indicative of the original data. In an alternative embodiment, there is provided an analog-to-digital converter operable for converting the modified analog input signal into a corresponding digital signal; a charge signal equalizer which initially transforms the digital signal into a corresponding digital charge signal, the equalizer performing waveform shaping of the digital charge signal in accordance with a predetermined signal response template; and a charge domain digital signal processor operable for recovering a digital bit stream from the digital charge domain signal which is indicative of the original data.

摘要翻译： 一种数据接收和处理通道，包括模拟信号处理电路，可操作用于以输入模拟信号的形式接收数据，并根据所选择的参数修改输入信号，以产生经修改的模拟输入信号。 根据一个实施例，提供一种电荷域信号均衡器，其初始将经修改的模拟输入信号转换成对应的模拟电荷域信号，均衡器根据预定的信号响应模板执行模拟电荷域信号的波形整形; 电荷域模数转换器，用于将模拟电荷域信号转换成对应的数字信号; 以及数字信号处理器，用于从指示原始数据的数字信号中恢复数字位流。 在替代实施例中，提供了可操作用于将修改的模拟输入信号转换成对应的数字信号的模数转换器; 电荷信号均衡器，其初始地将数字信号转换成相应的数字电荷信号，均衡器根据预定的信号响应模板执行数字电荷信号的波形整形; 以及电荷域数字信号处理器，用于从指示原始数据的数字电荷域信号中恢复数字位流。

公开(公告)号：US5646968A

公开(公告)日：1997-07-08

申请号：US560013

申请日：1995-11-17

申请人： Janos Kovacs ,  Ronald Kroesen ,  Kevin McCall

发明人： Janos Kovacs ,  Ronald Kroesen ,  Kevin McCall

IPC分类号： H03K3/0231 ,  H03K3/03 ,  H03L7/081 ,  H03L7/087 ,  H03L7/099 ,  H03L7/14 ,  H03D3/24

CPC分类号： H03K3/0231 ,  H03K3/03 ,  H03K3/0322 ,  H03L7/081 ,  H03L7/087 ,  H03L7/0996 ,  H03L7/14

摘要： A dynamic phase selector phase locked loop circuit includes: an A/D converter for receiving an input to be sampled; a phase detection circuit for determining the phase error between the input signal and a clock signal; a clock circuit, responsive to the phase detection circuit, for providing the clock signal to the A/D converter for timing the sampling of the input signal; the clock circuit including a delay circuit having a number of delay taps; and a phase selector circuit, responsive to the phase detection circuit, for initially gating the clock signals to the A/D converter from the clock circuit, and enabling one of the delay taps to dynamically adjust the phase of the clock signal and reduce the initial phase error.

摘要翻译： 动态相位选择器锁相环电路包括：A / D转换器，用于接收要采样的输入; 相位检测电路，用于确定输入信号和时钟信号之间的相位误差; 时钟电路，响应相位检测电路，用于将时钟信号提供给A / D转换器，用于对输入信号的采样进行定时; 所述时钟电路包括具有多个延迟抽头的延迟电路; 以及相位选择器电路，响应于相位检测电路，用于从时钟电路初始地将时钟信号选通到A / D转换器，并使得其中一个延迟抽头能够动态地调整时钟信号的相位并减少初始 相位误差。

公开(公告)号：US5495512A

公开(公告)日：1996-02-27

申请号：US314894

申请日：1994-09-29

申请人： Janos Kovacs ,  Ronald Kroesen

发明人： Janos Kovacs ,  Ronald Kroesen

IPC分类号： H03L7/08 ,  H03L7/087 ,  H03L7/093 ,  H03L7/099 ,  H03L7/107 ,  H03D3/24

CPC分类号： H03L7/107 ,  H03L7/093 ,  H03L7/099 ,  H03L2207/04

摘要： A phase locked loop system or other second order feedback system whose natural frequency scales with its output and whose damping factor remains constant includes a filter circuit having a scaling channel for scaling the error, an integrating channel for integrating the error, and a summing circuit for combining the scaled error and integrated error; an integrator circuit responsive to the summing circuit to produce an output signal, the gain of the integrator circuit being proportional to its output signal; and a control circuit for controlling the gain of the integrating channel proportional to the output signal and maintaining constant the ratio of and scaling the product of the unity gained frequency and the zero frequency of the feedback system to keep constant the damping factor and to scale the natural frequency of the feedback system with the output signal, respectively.

摘要翻译： 锁相环系统或其其它二阶反馈系统，其固有频率与其输出和其阻尼因子保持不变包括具有缩放误差缩放通道的滤波器电路，用于积分误差的积分通道和用于积分误差的积分通道 组合缩放误差和积分误差; 积分器电路，响应于求和电路产生输出信号，积分器电路的增益与其输出信号成比例; 以及控制电路，用于控制与输出信号成比例的积分通道的增益，并保持恒定的单位增益频率和反馈系统的零频率的乘积的比例并缩放，以保持阻尼因子的恒定并缩放 反馈系统的固有频率分别与输出信号。