公开(公告)号：US06366113B1

公开(公告)日：2002-04-02

申请号：US09716557

申请日：2000-11-20

申请人： Ki-whan Song

发明人： Ki-whan Song

IPC分类号： H03K30233

CPC分类号： H03K3/013 ,  H03K3/012 ,  H03K3/356139

摘要： A data receiver is provided for stabilizing a reference voltage to which input data is compared. The data receiver includes a differential amplification flip flop for comparing input data to a reference voltage in response to a clock signal, an amplifier for amplifying the results of the comparison, a latch for storing the logic level of the input data, and a counter coupling circuit for reducing the variation of the reference voltage caused by the operation of the differential amplification flip flop in response to an inverted clock signal. In the data receiver, the reference voltage is stably preserved without minimized variation. Also, there is substantially no consumption of direct current (DC) when the data receiver operates.

摘要翻译： 提供数据接收器用于稳定比较输入数据的参考电压。 数据接收机包括差分放大触发器，用于响应于时钟信号将输入数据与参考电压进行比较，用于放大比较结果的放大器，用于存储输入数据的逻辑电平的锁存器和反耦合器 电路，用于响应于反相时钟信号减小由差分放大触发器的操作引起的参考电压的变化。 在数据接收机中，参考电压被稳定地保持而没有最小化的变化。 此外，当数据接收器工作时，基本上不消耗直流电（DC）。

公开(公告)号：US08331162B2

公开(公告)日：2012-12-11

申请号：US12662222

申请日：2010-04-06

申请人： Jin-young Kim ,  Ki-whan Song

发明人： Jin-young Kim ,  Ki-whan Song

IPC分类号： G11C7/10

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

摘要： The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line.

摘要翻译： 半导体存储器件包括第一存储器单元阵列，其包括至少一个第一存储单元和与该至少一个第一存储单元对应的至少一个第二存储单元，连接至该至少一个第一存储单元的第一低位线， 连接到所述至少一个第二存储器单元的第一低互补位线，具有连接到所述第一低位线的第一端子的第一开关单元，具有连接到所述第一低互补位线的第一端子的第二开关单元， 连接到第一开关单元的第二端子的全局位线，连接到第二开关单元的第二端子的第一全局互补位线以及连接到第一全局位线和第一全局互补位置的多个感测放大单元 位线。

公开(公告)号：US20110163371A1

公开(公告)日：2011-07-07

申请号：US13047403

申请日：2011-03-14

申请人： Ki-whan Song ,  Byung-Gook Park

发明人： Ki-whan Song ,  Byung-Gook Park

IPC分类号： H01L29/772

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.

摘要翻译： 非易失性半导体存储器件包括从半导体衬底向上突出并具有相应顶表面和相对侧壁的多个柱，在柱的顶表面上的位线，并沿着第一方向连接一排柱，一对 在多个柱中的一个柱的相对的侧壁上并且在位线下方交叉的字线以及插入在该对字线中的相应一个字线和多个柱之一之间的一对存储层。 制造非易失性半导体存储器件的方法包括选择性地蚀刻半导体衬底以形成具有相对侧壁并沿着方向布置的多个条纹，沿着条纹的侧壁形成存储层和字线，选择性地蚀刻条纹以形成多个 并且形成连接柱子并跨越字线上方的位线。

公开(公告)号：US20090207648A1

公开(公告)日：2009-08-20

申请号：US12364119

申请日：2009-02-02

申请人： Ki-whan Song

发明人： Ki-whan Song

IPC分类号： G11C11/24 ,  G11C7/00

CPC分类号： G11C11/565 ,  G11C7/06 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2207/002

摘要： A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.

摘要翻译： 多级动态存储器件包括被分成主位线对和子位线对的位线对，连接在主位线对之间和子位线之间的第一和第二读出放大器 分别在主位对和子位对之间交叉耦合的对，第一和第二耦合电容器; 以及分别与第一和第二耦合电容器并联连接并且其电容由控制电压信号调节的第一和第二校正电容器。

公开(公告)号：US07525146B2

公开(公告)日：2009-04-28

申请号：US11520886

申请日：2006-09-14

申请人： Ki-whan Song ,  Byung-Gook Park

发明人： Ki-whan Song ,  Byung-Gook Park

IPC分类号： H01L29/94

CPC分类号： H01L27/115 ,  H01L27/11519 ,  H01L27/11568 ,  H01L29/792 ,  H01L29/7926

摘要： A nonvolatile semiconductor memory device includes a plurality of pillars protruding upward from a semiconductor substrate and having respective top surfaces and opposing sidewalls, a bit line on the top surfaces of the pillars and connecting a row of the pillars along a first direction, a pair of word lines on the opposing sidewalls of one of the plurality of pillars and crossing beneath the bit line, and a pair of memory layers interposed between respective ones of the pair of word lines and the one of the plurality of pillars. Methods of fabricating a nonvolatile semiconductor memory device include selectively etching a semiconductor substrate to form pluralities of stripes having opposing sidewalls and being arranged along a direction, forming memory layers and word lines along the sidewalls of the stripes selectively etching the stripes to form a plurality of pillars, and forming a bit line connecting the pillars and crossing above the word lines.

摘要翻译： 非易失性半导体存储器件包括从半导体衬底向上突出并具有相应顶表面和相对侧壁的多个柱，在柱的顶表面上的位线，并沿着第一方向连接一排柱，一对 在多个柱中的一个柱的相对的侧壁上并且在位线下方交叉的字线以及插入在该对字线中的相应一个字线和多个柱之一之间的一对存储层。 制造非易失性半导体存储器件的方法包括选择性地蚀刻半导体衬底以形成具有相对侧壁并沿着方向布置的多个条纹，沿着条纹的侧壁形成存储层和字线，选择性地蚀刻条纹以形成多个 并且形成连接柱子并跨越字线上方的位线。

公开(公告)号：US20070140005A1

公开(公告)日：2007-06-21

申请号：US11638002

申请日：2006-12-13

申请人： Ki-whan Song

发明人： Ki-whan Song

IPC分类号： G11C16/04 ,  G11C11/34 ,  G11C16/06

CPC分类号： G11C11/565 ,  G11C7/06 ,  G11C7/14 ,  G11C7/18 ,  G11C11/4091 ,  G11C11/4097 ,  G11C11/4099 ,  G11C2207/002

摘要： A multi-level dynamic memory device includes a bit line pair that is divided into a main bit line pair and a sub-bit line pair, first and second sense amplifiers that are connected between the main bit line pair and between the sub-bit line pair, first and second coupling capacitors that are cross-coupled between the main bit pair and the sub-bit pair, respectively; and first and second correction capacitors that are connected in parallel to the first and second coupling capacitors, respectively, and whose capacitance is adjusted by a control voltage signal.

摘要翻译： 多级动态存储器件包括被分成主位线对和子位线对的位线对，连接在主位线对之间和子位线之间的第一和第二读出放大器 分别在主位对和子位对之间交叉耦合的对，第一和第二耦合电容器; 以及分别与第一和第二耦合电容器并联连接并且其电容由控制电压信号调节的第一和第二校正电容器。

公开(公告)号：US07002242B2

公开(公告)日：2006-02-21

申请号：US09811666

申请日：2001-03-20

申请人： Ki-whan Song

发明人： Ki-whan Song

IPC分类号： H01L23/48 ,  H01L23/52 ,  H01L29/40

CPC分类号： H01L24/06 ,  H01L23/49816 ,  H01L23/49838 ,  H01L23/50 ,  H01L24/48 ,  H01L2224/04042 ,  H01L2224/05599 ,  H01L2224/06136 ,  H01L2224/32225 ,  H01L2224/4824 ,  H01L2224/73215 ,  H01L2224/85399 ,  H01L2924/00014 ,  H01L2924/01004 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/01068 ,  H01L2924/01082 ,  H01L2924/15311 ,  H01L2924/30107 ,  H01L2224/45099 ,  H01L2924/00012

摘要： A ball grid array package semiconductor device having improved power line routing. The BGA package semiconductor device includes a semiconductor chip having a plurality of pads along its center, a substrate having a slot of a predetermined size along its center, and a signal line plane including a signal line pattern and a plurality of ball mounts on its one side, with the semiconductor chip being mounted on the other side. A bonding material is inserted between the semiconductor chip and the substrate to fix the semiconductor chip to the substrate. A plurality of balls are mounted on the plurality of ball mounts to be connected to an external circuit. The signal line plane is divided into two or more signal line planes including a first line plane and a second line plane. Lines for the first power are formed only on the first signal line plane, and lines for the second power are formed only on the second signal line plane.

摘要翻译： 具有改进的电力线路由的球栅阵列封装半导体器件。 BGA封装半导体器件包括其中心具有多个焊盘的半导体芯片，沿其中心具有预定尺寸的槽的衬底以及包括信号线图案的信号线平面和在其一个上的多个球座 半导体芯片安装在另一侧。 在半导体芯片和基板之间插入接合材料，以将半导体芯片固定到基板上。 多个球安装在多个球座上以连接到外部电路。 信号线平面被分成包括第一线平面和第二线平面的两个或多个信号线平面。 用于第一功率的线仅形成在第一信号线平面上，并且用于第二功率的线仅形成在第二信号线平面上。

公开(公告)号：US06184701B2

公开(公告)日：2001-02-06

申请号：US09320889

申请日：1999-05-27

申请人： Chang-hyun Kim ,  Ki-whan Song

发明人： Chang-hyun Kim ,  Ki-whan Song

IPC分类号： H03K1716

CPC分类号： H03K19/003

摘要： Integrated circuit devices having metastability protection circuits therein include a main active circuit and a metastability detection/prevention circuit. The main active circuit may comprise a comparator, a sense amplifier, a differential amplifier or a voltage generating circuit, for example. The metastability detection/prevention circuit performs the function of detecting whether an output of the main active circuit has been disposed in a metastable state for a duration in excess of a transition duration. The output of the main active circuit may be considered as being in a metastable state if a potential of the output signal equals VMS, where VMS is in a range between VIL, and VIH. If the output signal has been in a metastable state for a duration in excess of the transition duration, then the metastability detection/prevention circuit will generate a control signal at a designated logic level. This control signal is provided as an input to the main active circuit and causes the output of the main active circuit to be driven out of the metastable state (i.e., to a logic 1 or 0 level). In this manner, prolonged metastability can be prevented even if the values of the input signals to the main active circuit would otherwise dispose the output in a metastable state.

摘要翻译： 其中具有亚稳态保护电路的集成电路器件包括主有源电路和亚稳态检测/防止电路。 主有源电路可以包括例如比较器，读出放大器，差分放大器或电压产生电路。 亚稳定性检测/防止电路执行检测主有源电路的输出是否已经在亚稳态中超过过渡持续时间的持续时间的功能。 如果输出信号的电位等于VMS，则主有源电路的输出可以被认为处于亚稳态，其中VMS在VIL和VIH之间的范围内。 如果输出信号已经处于超过转换持续时间的持续时间的亚稳态，则亚稳检测/防止电路将以指定的逻辑电平产生控制信号。 该控制信号被提供给主有源电路的输入，并且使得主有源电路的输出被驱动到亚稳态（即，到逻辑1或0电平）之外。 以这种方式，即使主动作电路的输入信号的值以其他方式将输出置于亚稳态，也可以防止延长的亚稳态。

公开(公告)号：US07990769B2

公开(公告)日：2011-08-02

申请号：US12547078

申请日：2009-08-25

申请人： Ki-whan Song

发明人： Ki-whan Song

IPC分类号： G11C16/04

CPC分类号： H01L29/66833 ,  G11C16/10 ,  H01L29/66825 ,  H01L29/7881 ,  H01L29/792

摘要： A first channel in the substrate underlying a trap gate is biased to cause trapping of holes or electrons in the trap gate and thereby program the memory device to a programmed state. A second channel in the substrate underlying the trap gate and transverse to the first channel is biased to sense the programmed state. For example, biasing a first channel in the substrate underlying the trap gate to cause trapping of holes or electrons in the trap gate and thereby program the memory device to a programmed state may include applying voltages to a first source/drain region and first gate on a first side of the trap gate and to a second source/drain region and a second gate on a second side of the trap gate, and biasing a second channel in the substrate underlying the trap gate and transverse to the first channel to sense the programmed state may include applying voltages to a third source/drain region on a third side of the trap gate and to a fourth source/drain region on a fourth side of the trap gate.

摘要翻译： 位于陷阱栅极下方的衬底中的第一通道被偏置以引起陷阱栅极中的空穴或电子的捕获，从而将存储器件编程到编程状态。 位于陷阱门下方并横向于第一通道的衬底中的第二通道被偏置以感测编程状态。 例如，偏置陷阱栅极下方的衬底中的第一通道以引起陷阱栅极中的空穴或电子的俘获，从而将存储器件编程到编程状态可包括将电压施加到第一源/漏区和第一栅上 陷阱栅极的第一侧和陷阱栅极的第二侧上的第二源极/漏极区域和第二栅极，以及偏置陷阱栅极下方并横向于第一通道的衬底中的第二通道，以感测编程的 状态可以包括将电压施加到陷阱栅极的第三侧上的第三源极/漏极区域和陷阱栅极的第四侧上的第四源极/漏极区域。

公开(公告)号：US20110013464A1

公开(公告)日：2011-01-20

申请号：US12662222

申请日：2010-04-06

申请人： Jin-young Kim ,  Ki-whan Song

发明人： Jin-young Kim ,  Ki-whan Song

IPC分类号： G11C7/10 ,  G11C7/00

CPC分类号： G11C7/18 ,  G11C7/12 ,  G11C11/4094 ,  G11C11/4097

摘要： The semiconductor memory device includes a first memory cell array including at least one first memory cell and at least one second memory cell corresponding to the at least one first memory cell, a first low bit line connected to the at least one first memory cell, a first low complementary bit line connected to the at least one second memory cell, a first switch unit having a first terminal connected to the first low bit line, a second switch unit having a first terminal connected to the first low complementary bit line, a first global bit line connected to a second terminal of the first switch unit, a first global complementary bit line connected to a second terminal of the second switch unit, and a plurality of sensing amplifying units connected to the first global bit line and the first global complementary bit line.

摘要翻译： 半导体存储器件包括第一存储器单元阵列，其包括至少一个第一存储单元和与该至少一个第一存储单元对应的至少一个第二存储单元，连接至该至少一个第一存储单元的第一低位线， 连接到所述至少一个第二存储器单元的第一低互补位线，具有连接到所述第一低位线的第一端子的第一开关单元，具有连接到所述第一低互补位线的第一端子的第二开关单元， 连接到第一开关单元的第二端子的全局位线，连接到第二开关单元的第二端子的第一全局互补位线以及连接到第一全局位线和第一全局互补位置的多个感测放大单元 位线。