公开(公告)号：US11776651B2

公开(公告)日：2023-10-03

申请号：US17202432

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Masanobu Shirakawa ,  Hideki Yamada ,  Marie Takada

IPC: G11C29/44 ,  G11C29/42 ,  G11C29/20 ,  G11C29/12 ,  G11C29/18

CPC classification number: G11C29/42 ,  G11C29/12005 ,  G11C29/20 ,  G11C2029/1202 ,  G11C2029/1204 ,  G11C2029/1802

Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.

公开(公告)号：US11742026B2

公开(公告)日：2023-08-29

申请号：US17869081

申请日：2022-07-20

Applicant: KIOXIA CORPORATION

Inventor： Hideki Yamada ,  Marie Takada ,  Masanobu Shirakawa

IPC: G06F3/06 ,  G11C16/10 ,  G11C16/04 ,  G11C11/56

CPC classification number: G11C16/10 ,  G06F3/061 ,  G06F3/0658 ,  G06F3/0659 ,  G06F3/0679 ,  G11C16/0483 ,  G11C11/5628

Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

公开(公告)号：US11574686B2

公开(公告)日：2023-02-07

申请号：US17190638

申请日：2021-03-03

Applicant: Kioxia Corporation

Inventor： Hideki Yamada ,  Masanobu Shirakawa

IPC: G11C16/26 ,  G11C16/04 ,  G11C16/08 ,  H01L27/11556 ,  G11C11/56

Abstract: According to the one embodiment, a memory system includes a semiconductor memory device and a memory controller. The semiconductor memory device includes: first and second memory cells stacked above a substrate; a first word line coupled to the first and second memory cells; a first bit line coupled to the first memory cell; and a second bit line coupled to the second memory cell. A first state read operation includes a first read operation for reading data from the first memory cell and a second read operation for reading data from the second memory cell. A first read voltage is applied to the first word line during a first period for executing the first read operation, and a second read voltage is applied to the first word line during a second period for executing the second read operation.

公开(公告)号：US11514986B2

公开(公告)日：2022-11-29

申请号：US17202627

申请日：2021-03-16

Applicant: Kioxia Corporation

Inventor： Kengo Kurose ,  Masanobu Shirakawa ,  Hideki Yamada ,  Marie Takada

IPC: G11C16/04 ,  G11C16/16 ,  G11C11/56 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06 ,  H01L27/11582 ,  H01L27/11556

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.