公开(公告)号：US12131637B2

公开(公告)日：2024-10-29

申请号：US17705766

申请日：2022-03-28

Applicant: KIOXIA CORPORATION

Inventor： Marie Takada ,  Masanobu Shirakawa

IPC: G08G1/0967 ,  G06T7/70 ,  G06V20/58 ,  G08G1/01 ,  G08G1/04 ,  G08G1/137

CPC classification number: G08G1/0967 ,  G06T7/70 ,  G06V20/58 ,  G08G1/0112 ,  G08G1/0141 ,  G08G1/04 ,  G08G1/096716 ,  G08G1/096741 ,  G08G1/096775 ,  G08G1/137 ,  G06T2207/30261

Abstract: A driving support system includes a first monitoring device on a first object, the first monitoring device having a first controller, a first camera, and a first display, a second monitoring device on a second object, the second monitoring device having a second controller and a second camera, and a server in communication with the first and second monitoring devices. The first and second controllers each detect a target in images acquired from the respective first or second camera, calculate target information for the target, and transmit the target information to the server. The server generates list information including the target information the first and second monitoring devices, and transmits the list information to the first and second monitoring devices. The first controller further generates a map according to the list information received from the server, and displays the map on the first display.

公开(公告)号：US11875063B2

公开(公告)日：2024-01-16

申请号：US18082759

申请日：2022-12-16

Applicant: KIOXIA CORPORATION

Inventor： Marie Takada ,  Masanobu Shirakawa ,  Tsukasa Tokutomi

IPC: G11C29/00 ,  G06F3/06 ,  G11C16/26 ,  G11C16/10 ,  G11C16/16 ,  G11C16/08 ,  G06F11/10 ,  G11C29/52 ,  G11C16/04 ,  G11C11/56 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679 ,  G06F11/1068 ,  G11C16/0483 ,  G11C16/08 ,  G11C16/10 ,  G11C16/16 ,  G11C16/26 ,  G11C29/52 ,  G11C11/5621 ,  G11C11/5671 ,  H10B41/27 ,  H10B41/35 ,  H10B43/27 ,  H10B43/35

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The memory system is capable of executing a first operation and a second operation. In the first operation, the controller issues a first command sequence, the semiconductor memory applies a first voltage to a first word line and applies a second voltage to a second word line to read data from the first memory, and the read data is transmitted to the controller from the semiconductor memory. In the second operation, the controller issues a second command sequence, the semiconductor memory applies a third voltage to the first word line and applies a fourth voltage to the second word line, and data held in the memory cell array is left untransmitted to the controller.

公开(公告)号：US11869601B2

公开(公告)日：2024-01-09

申请号：US18053271

申请日：2022-11-07

Applicant: Kioxia Corporation

Inventor： Kenji Sakurada ,  Naomi Takeda ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06 ,  G11C16/34 ,  H10B69/00

CPC classification number: G11C16/26 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/3459 ,  H10B69/00

Abstract: A memory system includes a first memory cell array which is a nonvolatile memory cell array, a controller configured to control read and write of data, a first data latch group used for input and output of the data between the controller and the first memory cell array, and at least one second data latch group in which stored data is maintained when the data is read from the first memory cell array by the controller. The controller is configured to store management information in the at least one second data latch group when or before executing a read process for the data from the first memory cell array, the management information being in a second memory cell array and used for read of the data.

公开(公告)号：US11790986B2

公开(公告)日：2023-10-17

申请号：US17874926

申请日：2022-07-27

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada

IPC: G11C11/00 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G11C16/30 ,  G11C16/08 ,  H10B43/27 ,  H10B43/35

CPC classification number: G11C11/5642 ,  G06F11/1068 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/08 ,  G11C16/30 ,  G11C2211/563 ,  G11C2211/5642 ,  H10B43/27 ,  H10B43/35

Abstract: A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.

公开(公告)号：US11537465B2

公开(公告)日：2022-12-27

申请号：US17174399

申请日：2021-02-12

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Masamichi Fujiwara ,  Kazumasa Yamamoto ,  Naoaki Kokubun ,  Tatsuro Hitomi ,  Hironori Uchikawa

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/15

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.

公开(公告)号：US11430520B2

公开(公告)日：2022-08-30

申请号：US16802428

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Hideki Yamada ,  Marie Takada ,  Masanobu Shirakawa

IPC: G11C16/10 ,  G11C16/04 ,  G06F3/06 ,  G11C11/56

Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

公开(公告)号：US12300343B2

公开(公告)日：2025-05-13

申请号：US18053896

申请日：2022-11-09

Applicant: Kioxia Corporation

Inventor： Marie Takada ,  Masanobu Shirakawa ,  Hideki Yamada ,  Ryo Yamaki

IPC: G11C16/06 ,  G11C11/4074 ,  G11C11/4096 ,  G11C29/52

Abstract: A memory system includes a nonvolatile memory including memory cells each configured to store first and second bits, and a memory controller. The memory controller is configured to: read first data by using a first voltage to a first read process that reads data corresponding to the first bit from the memory cells; read second data by using a second voltage to a second read process that reads data corresponding to the second bit from the memory cells; in a case where an error correction process of the first data is successful, determine a third voltage, based on the first data and third data that is obtained by error-correcting the first data; and update a first read voltage that is used to the first read process, from the first voltage to the third voltage.

公开(公告)号：US12117902B2

公开(公告)日：2024-10-15

申请号：US18324226

申请日：2023-05-26

Applicant: KIOXIA CORPORATION

Inventor： Kengo Kurose ,  Masanobu Shirakawa ,  Marie Takada

IPC: G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

CPC classification number: G06F11/1068 ,  G11C11/5642 ,  G11C11/5671 ,  G11C16/0483 ,  G11C16/26

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

公开(公告)号：US11923029B2

公开(公告)日：2024-03-05

申请号：US18180944

申请日：2023-03-09

Applicant: Kioxia Corporation

Inventor： Marie Takada ,  Masanobu Shirakawa

IPC: G11C29/42 ,  G11C29/12 ,  G11C29/18 ,  G11C29/44 ,  G11C29/50

CPC classification number: G11C29/42 ,  G11C29/1201 ,  G11C29/18 ,  G11C29/4401 ,  G11C29/50004 ,  G11C2029/1202

Abstract: According to one embodiment, a memory system includes: a controller configured to execute an error correction process on first data read from a first area at a first address of a memory device and determine a read level used for reading data at the first address according to a result of the correction process. The controller executes the correction process on first frame data of the first data. When the correction process on the first frame data has failed, the controller executes the correction process on second frame data of the first data. When the correction process on the second frame data has succeeded, the controller determines the read level based on a result of comparison between the second frame data and a result of the correction process on the second frame data.

公开(公告)号：US11892907B2

公开(公告)日：2024-02-06

申请号：US17984309

申请日：2022-11-10

Applicant: Kioxia Corporation

Inventor： Tsukasa Tokutomi ,  Masanobu Shirakawa ,  Marie Takada ,  Masamichi Fujiwara ,  Kazumasa Yamamoto ,  Naoaki Kokubun ,  Tatsuro Hitomi ,  Hironori Uchikawa

IPC: H03M13/00 ,  G06F11/10 ,  H03M13/11 ,  H03M13/37 ,  H03M13/29 ,  H03M13/15

CPC classification number: G06F11/1068 ,  G06F11/1012 ,  G06F11/1048 ,  H03M13/1105 ,  H03M13/1108 ,  H03M13/1111 ,  H03M13/152 ,  H03M13/2906 ,  H03M13/3715 ,  H03M13/6505

Abstract: In general, according to an embodiment, a memory system includes a memory device including a memory cell; and a controller. The controller is configured to: receive first data from the memory cell in a first data reading; receive second data from the memory cell in a second data reading that is different from the first data reading; convert a first value that is based on the first data and the second data, to a second value in accordance with a first relationship; and convert the first value to a third value in accordance with a second relationship that is different from the first relationship.