公开(公告)号：US20230047861A1

公开(公告)日：2023-02-16

申请号：US17976566

申请日：2022-10-28

Applicant: Kioxia Corporation

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA

IPC: G11C16/16 ,  G11C11/56 ,  G11C16/04 ,  G11C16/10 ,  G11C16/26 ,  G11C16/34 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The semiconductor memory device includes a first memory cell configured to store data. The controller is configured to output a first parameter and a first command. The first parameter relates to an erase voltage for a first erase operation with respect to the first memory cell. The first command instructs the first erase operation. The controller outputs the first command after outputting the first parameter to the semiconductor memory device.

公开(公告)号：US20220270687A1

公开(公告)日：2022-08-25

申请号：US17743998

申请日：2022-05-13

Applicant: KIOXIA CORPORATION

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

公开(公告)号：US20220270678A1

公开(公告)日：2022-08-25

申请号：US17738069

申请日：2022-05-06

Applicant: KIOXIA CORPORATION

Inventor： Tomonori TAKAHASHI ,  Masanobu SHIRAKAWA ,  Osamu TORII ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/26 ,  G11C16/08 ,  G11C16/04

Abstract: According to one embodiment, a semiconductor memory device includes: a memory cell configured to hold 5-bit data; a word line coupled to the memory cell; and a row decoder configured to apply first to 31st voltages to the word line. A first bit of the 5-bit data is established by reading operations using first to sixth voltages. A second bit of the 5-bit data is established by reading operations using seventh to twelfth voltages. A third bit of the 5-bit data is established by reading operations using thirteenth to eighteenth voltages. A fourth bit of the 5-bit data is established by reading operations using nineteenth to 25th voltages. A fifth bit of the 5-bit data is established by reading operations using 26th to 31st voltages.

公开(公告)号：US20220245030A1

公开(公告)日：2022-08-04

申请号：US17718969

申请日：2022-04-12

Applicant: KIOXIA CORPORATION

Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

公开(公告)号：US20210082510A1

公开(公告)日：2021-03-18

申请号：US16802428

申请日：2020-02-26

Applicant: KIOXIA CORPORATION

Inventor： Hideki YAMADA ,  Marie TAKADA ,  Masanobu SHIRAKAWA

IPC: G11C16/10 ,  G11C16/04 ,  G06F3/06

Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

公开(公告)号：US20230395178A1

公开(公告)日：2023-12-07

申请号：US18453567

申请日：2023-08-22

Applicant: KIOXIA CORPORATION

Inventor： Masanobu SHIRAKAWA ,  Hideki YAMADA ,  Marie TAKADA

IPC: G11C29/42 ,  G11C29/20 ,  G11C29/12

CPC classification number: G11C29/42 ,  G11C29/20 ,  G11C29/12005 ,  G11C2029/1802

Abstract: A memory system according to an embodiment includes a memory device, and a memory controller. The memory device includes first and second memory cells, a first word line, and first and second bit lines. The first and second memory cells are provided in first and second layers, respectively. The first word line is coupled to the first memory cell and the second memory cell. The first bit line is coupled to the first memory cell. The second bit line is coupled to the second memory cell. The memory controller includes a storage circuit capable of storing a correction value table. The correction value table is configured to store a first correction value of a read voltage associated with the first layer and a second correction voltage of a read voltage associated with the second layer.

公开(公告)号：US20230069906A1

公开(公告)日：2023-03-09

申请号：US17985224

申请日：2022-11-11

Applicant: Kioxia Corporation

Inventor： Marie TAKADA ,  Masanobu Shirakawa

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G06F3/06

Abstract: A memory device according to one embodiment includes a memory cell array, bit lines, amplifier units, a controller, and a register. The memory cell array includes a memory cell that stores data nonvolatilely. The bit lines are connected to the memory cell array. The sense amplifier units are connected to the bit lines, respectively. The controller performs a write operation. The register stores status information of the write operation. The memory cell array includes a first storage region specified by a first address. The plurality of sense amplifier modules include a buffer region capable of storing data.

公开(公告)号：US20220375516A1

公开(公告)日：2022-11-24

申请号：US17874926

申请日：2022-07-27

Applicant: Kioxia Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA

IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G06F11/10

Abstract: A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.

公开(公告)号：US20220351780A1

公开(公告)日：2022-11-03

申请号：US17869081

申请日：2022-07-20

Applicant: KIOXIA CORPORATION

Inventor： Hideki YAMADA ,  Marie TAKADA ,  Masanobu SHIRAKAWA

IPC: G11C16/10 ,  G11C16/04 ,  G06F3/06

Abstract: In connection with a write operation, a memory controller transmits a first command sequence to a memory chip, thereby causing the memory chip to execute a first-stage program operation that includes a first operation and a first part of a second operation after the first operation, and a second command sequence to the memory chip after the first-stage program operation is executed, thereby causing the memory chip to execute a second-stage program operation that includes a second part of the second operation and no part of the first operation. During the first operation, a program voltage is applied a plurality of times while increasing the program voltage each of the times by a first step size. During the second operation, the program voltage is applied a plurality of times while increasing the program voltage each of the times by a second step size smaller than the first step size.

公开(公告)号：US20220130468A1

公开(公告)日：2022-04-28

申请号：US17568336

申请日：2022-01-04

Applicant: Kioxia Corporation

Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Shohei ASAMI ,  Masamichi FUJIWARA

IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06

Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.