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    MEMORY SYSTEM
    1.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230360714A1

    公开(公告)日：2023-11-09

    申请号：US18354300

    申请日：2023-07-18

    Applicant: KIOXIA CORPORATION

    Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Kiwamu WATANABE ,  Kengo KUROSE

    IPC: G11C29/12 ,  G11C16/26 ,  G11C16/08 ,  G06F3/06

    CPC classification number: G11C29/12 ,  G11C16/26 ,  G11C16/08 ,  G06F3/0619 ,  G06F3/0673 ,  G06F3/0658 ,  G11C2029/1202

    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

    MULTI-BIT MEMORY SYSTEM WITH ADAPTIVE READ VOLTAGE CONTROLLER
    2.
    发明申请
    MULTI-BIT MEMORY SYSTEM WITH ADAPTIVE READ VOLTAGE CONTROLLER 有权

    公开(公告)号：US20220270687A1

    公开(公告)日：2022-08-25

    申请号：US17743998

    申请日：2022-05-13

    Applicant: KIOXIA CORPORATION

    Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA

    IPC: G11C16/26 ,  G11C16/34 ,  G11C16/04 ,  G11C11/56

    Abstract: According to an embodiment, a semiconductor memory, on receiving a first command, applies a voltage within a first range and a voltage within a second range to a word line and reads a first bit from a memory cell, and, on receiving a second command, applies a voltage within a third range to the word line and reads a second bit from the memory cell. The controller issues the first command a plurality of times and changes the voltages to be applied to the word line within the first range and the second range in accordance with the plurality of first commands, specifies a first and second voltage within the first and the second range, respectively, and estimates a third voltage within the third range. The voltage applied to read the second bit is the estimated third voltage.

    SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM INCLUDING SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER
    3.
    发明申请
    SEMICONDUCTOR STORAGE DEVICE AND MEMORY SYSTEM INCLUDING SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER 有权

    公开(公告)号：US20220375516A1

    公开(公告)日：2022-11-24

    申请号：US17874926

    申请日：2022-07-27

    Applicant: Kioxia Corporation

    Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA

    IPC: G11C11/56 ,  G11C16/04 ,  G11C16/26 ,  G06F11/10

    Abstract: A memory system is provided, including a semiconductor storage device including memory cells that can store data of n bits, and a word line connected to the cells; and a memory controller to control the device and being configured to send a first read request, in response to which the device can perform a first read operation of reading first data out of the cells with a first voltage applied to the word line, to send a second read request, in response to which the device can perform a second read operation of reading second data out of the cells with a second voltage within a first voltage range and a third voltage within a second voltage range applied to the word line, perform a first logical operation of logically processing the first and the second data, and send third data generated by the first logical operation to the controller.

    MEMORY SYSTEM
    4.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220130468A1

    公开(公告)日：2022-04-28

    申请号：US17568336

    申请日：2022-01-04

    Applicant: Kioxia Corporation

    Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Shohei ASAMI ,  Masamichi FUJIWARA

    IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06

    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

    METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY
    7.
    发明申请
    METHOD OF CONTROLLING A SEMICONDUCTOR MEMORY 有权

    公开(公告)号：US20220208282A1

    公开(公告)日：2022-06-30

    申请号：US17696339

    申请日：2022-03-16

    Applicant: KIOXIA CORPORATION

    Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA

    IPC: G11C16/34 ,  G11C11/56 ,  G11C16/26 ,  G06F11/10 ,  G11C29/52 ,  G11C16/10

    Abstract: According to one embodiment, a controller is configured to write four-bit data in each of memory cells, and read first data item from the memory cells through application of a first voltage to a word line. The controller is configured to read second data items by repeating a first operation of reading data including data of respective first bits of the memory cells through application of two voltages to the word line at different timings while changing the two voltages in each first operation from the two voltages in another first operation. The controller is configured to mask part of each of the second data items using the first data.

    MEMORY SYSTEM
    9.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240363174A1

    公开(公告)日：2024-10-31

    申请号：US18768178

    申请日：2024-07-10

    Applicant: KIOXIA CORPORATION

    Inventor： Masanobu SHIRAKAWA ,  Tsukasa TOKUTOMI ,  Marie TAKADA

    IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  H10B43/27 ,  H10B43/35

    CPC classification number: G11C16/26 ,  G11C11/5671 ,  G11C16/0483 ,  H10B43/27 ,  H10B43/35

    Abstract: According to one embodiment, a memory system includes a semiconductor memory device and a controller. The device includes a plurality of memory cells capable of storing at least first to third data and a word line coupled to the plurality of memory cells. The first data is determined by a first read operation including a first read level. The second data is determined by a second read operation including a second read level. The third data is determined by a third read operation including a third read level. The controller controls the semiconductor memory device to perform a forth read operation including the first and second read levels in a search operation for first to third read voltages corresponding to the first to third read levels, respectively.

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