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    MEMORY SYSTEM
    1.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20250004880A1

    公开(公告)日：2025-01-02

    申请号：US18882152

    申请日：2024-09-11

    Applicant: KIOXIA CORPORATION

    Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Marie TAKADA

    IPC: G06F11/10 ,  G11C11/56 ,  G11C16/04 ,  G11C16/26

    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

    MEMORY SYSTEM
    4.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230360714A1

    公开(公告)日：2023-11-09

    申请号：US18354300

    申请日：2023-07-18

    Applicant: KIOXIA CORPORATION

    Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Kiwamu WATANABE ,  Kengo KUROSE

    IPC: G11C29/12 ,  G11C16/26 ,  G11C16/08 ,  G06F3/06

    CPC classification number: G11C29/12 ,  G11C16/26 ,  G11C16/08 ,  G06F3/0619 ,  G06F3/0673 ,  G06F3/0658 ,  G11C2029/1202

    Abstract: A memory system according to an embodiment includes a semiconductor memory, and a memory controller. The semiconductor memory comprises memory cells and word lines. Each of the word lines is connected to the memory cells. The memory controller executes a patrol operation including a read operation of the semiconductor memory. The word lines are classified into one of first and second groups. The memory controller executes patrol operations in which the word lines are respectively selected in a first patrol period and, in a second patrol period subsequent to the first patrol period, executes a patrol operation in which the word line included in the first group is selected and omits a patrol operation in which the word line included in the second group is selected.

    MEMORY SYSTEM
    5.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20230297473A1

    公开(公告)日：2023-09-21

    申请号：US18324226

    申请日：2023-05-26

    Applicant: KIOXIA CORPORATION

    Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Marie TAKADA

    IPC: G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

    CPC classification number: G06F11/1068 ,  G11C16/0483 ,  G11C11/5671 ,  G11C16/26 ,  G11C11/5642

    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

    MEMORY SYSTEM
    7.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220245030A1

    公开(公告)日：2022-08-04

    申请号：US17718969

    申请日：2022-04-12

    Applicant: KIOXIA CORPORATION

    Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Marie TAKADA

    IPC: G06F11/10 ,  G11C16/04 ,  G11C11/56 ,  G11C16/26

    Abstract: According to an embodiment, a memory controller obtains first data in a first page using a first voltage, obtains a first shift amount based on a first and second number. The first and second numbers represent numbers of bits each of which has different values in a first and second manner between the first data and first expected data. The controller obtains second data in the second page using a second voltage and a second shift amount, and obtains a third shift amount based on a third and fourth number, the third and fourth numbers respectively represent numbers of bits each of which has different values in the first and second manner between the second data and second expected data.

    MEMORY SYSTEM
    8.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220066688A1

    公开(公告)日：2022-03-03

    申请号：US17201092

    申请日：2021-03-15

    Applicant: Kioxia Corporation

    Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA ,  Naomi TAKEDA ,  Hideki YAMADA

    IPC: G06F3/06

    Abstract: According to one embodiment, a shift register memory writes data having a first size corresponding to a capacity of a block to a plurality of layers of a plurality of data storing shift strings included in the block, in response to a first command sequence specifying a first write mode from a controller. In response to a second command sequence specifying a second write mode from the controller, the shift register memory writes data having a second size smaller than the capacity of the block to the plurality of layers of one or more first data storing shift strings of the plurality of data storing shift strings, without writing data to each of other data storing shift strings except the one or more first data storing shift strings.

    MEMORY SYSTEM
    9.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210357289A1

    公开(公告)日：2021-11-18

    申请号：US17387890

    申请日：2021-07-28

    Applicant: KIOXIA CORPORATION

    Inventor： Kengo KUROSE ,  Masanobu SHIRAKAWA

    IPC: G06F11/10 ,  G11C16/26 ,  G11C11/56 ,  G11C16/04

    Abstract: A memory system includes a semiconductor storage device and a memory controller including a storage circuit that stores correction value for read voltages in association with the word line, and a control circuit that reads data from the memory cells, performs a correction operation on the read data to determine a number of error bits therein, determines the correction value for each read voltage based on the number of error bits and a ratio of a lower tail fail bit count and an upper tail fail bit count, and stores the correction values for the read voltages in the storage circuit. The lower tail fail bit count represents the number of memory cells in a first state having threshold voltages of an adjacent state, and the upper tail fail bit count represents the number of memory cells in the adjacent state having threshold voltages of the first state.

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