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    MEMORY SYSTEM
    1.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220130468A1

    公开(公告)日：2022-04-28

    申请号：US17568336

    申请日：2022-01-04

    Applicant: Kioxia Corporation

    Inventor： Tsukasa TOKUTOMI ,  Masanobu SHIRAKAWA ,  Marie TAKADA ,  Shohei ASAMI ,  Masamichi FUJIWARA

    IPC: G11C16/26 ,  G11C16/04 ,  G06F3/06

    Abstract: According to one embodiment, a memory system includes a semiconductor memory and a controller. The semiconductor memory includes first to fourth word lines and first to fourth memory cells. The controller is configured to issue first and second instructions. The controller is further configured to execute a first operation to obtain a first read voltage based on a threshold distribution of the first memory cell, and a second operation to read data from the second memory cell.

    MEMORY SYSTEM AND MEMORY DEVICE
    2.
    发明申请
    MEMORY SYSTEM AND MEMORY DEVICE 有权

    公开(公告)号：US20250130938A1

    公开(公告)日：2025-04-24

    申请号：US18882292

    申请日：2024-09-11

    Applicant: Kioxia Corporation

    Inventor： Kazutaka TAKIZAWA ,  Yuki KAMIJO ,  Takehiko AMAKI ,  Shohei ASAMI ,  Shunichi IGAHARA

    IPC: G06F12/02

    Abstract: A memory system according to one embodiment includes a memory device and a memory controller. The memory device includes memory cells. The memory controller executes a tracking operation. In the tracking operation, the memory controller is configured to cause the memory device to execute a plurality of times of read operations using a plurality of read levels. In the tracking operation, the memory controller is further configured to set a first voltage difference between two adjacent read levels of the read levels in a fourth voltage range lower than a first voltage in a third voltage range and a second voltage difference between two adjacent read levels of the read levels in a fifth voltage range higher than the first voltage in the third voltage range. The first and second voltage differences are different from each other.

    MEMORY SYSTEM
    6.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20210295941A1

    公开(公告)日：2021-09-23

    申请号：US17022274

    申请日：2020-09-16

    Applicant: Kioxia Corporation

    Inventor： Shohei ASAMI ,  Takehiko AMAKI

    IPC: G11C29/42 ,  G11C16/10 ,  G11C16/04 ,  G11C29/44 ,  G11C29/50 ,  G11C29/12 ,  G11C16/26

    Abstract: According to one embodiment, a memory system includes: a memory chip including a first memory block and first word lines, the first memory block including a first memory string which includes first memory cells that are coupled in series, the first word lines being respectively coupled to gates of the first memory cells; a memory controller coupled to an external device, controlling the memory chip, and capable of performing an error checking and correcting process of data. When a write instruction is received from the external device, the memory controller is configured to perform a write operation on a second memory cell which is one of the first memory cells, and to perform a read verify operation including a read process and the ECC process on a third memory cell which is one of the first memory cells.

    MEMORY SYSTEM
    9.
    发明公开
    MEMORY SYSTEM 审中-公开

    公开(公告)号：US20240005969A1

    公开(公告)日：2024-01-04

    申请号：US18068914

    申请日：2022-12-20

    Applicant: Kioxia Corporation

    Inventor： Shohei ASAMI ,  Yoshihisa KOJIMA

    IPC: G11C7/10 ,  G11C29/52

    CPC classification number: G11C7/1096 ,  G11C7/1069 ,  G11C29/52

    Abstract: According to one embodiment, a memory system includes a semiconductor memory, a controller, and a first circuit. The semiconductor memory includes a nonvolatile memory cell. The controller is configured to cause the semiconductor memory to execute first and second write operations. The first write operation writes a first bit into the memory cell. The second write operation writes first data based on the first bit and a second bit into the memory cell. The first circuit checks whether or not the first bit includes a bit error. The controller is configured to cause the semiconductor memory to execute, in the second write operation, writing of the first data including the second bit and a third bit obtained by correcting the bit error of the first bit, in a case that the first bit includes the bit error.

    MEMORY SYSTEM
    10.
    发明申请
    MEMORY SYSTEM 有权

    公开(公告)号：US20220392523A1

    公开(公告)日：2022-12-08

    申请号：US17888065

    申请日：2022-08-15

    Applicant: Kioxia Corporation

    Inventor： Shohei ASAMI ,  Toshikatsu HIDA ,  Riki SUZUKI

    IPC: G11C11/406 ,  G11C16/16 ,  G11C16/10 ,  G11C16/34

    Abstract: According to one embodiment, a memory system includes a non-volatile memory and a memory controller. The non-volatile memory includes a plurality of groups, each including a plurality of memory cells. The memory controller is configured to determine whether to execute a refresh process for a first group based on whether a first temperature in a write process for the first group and a second temperature after the write process for the first group satisfy a first condition.

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