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公开(公告)号：US20050161768A1
公开(公告)日：2005-07-28
申请号：US11016810
申请日：2004-12-21
IPC分类号： H01L29/78 , H01L27/04 , H01L27/088 , H01L29/423 , H01L29/739 , H01L31/113
CPC分类号： H01L29/7397 , H01L29/4232 , H01L29/42372 , H01L29/7395
摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.
摘要翻译： 半导体器件包括具有第一表面和第二表面的第一导电类型的第一基底层; 形成在第一表面上的第二导电类型的第二基层; 通过经由栅极绝缘膜将导电材料嵌入多个沟槽而形成的第一和第二栅电极，所述多个沟槽形成为使得沟槽的底部到达第一基底层; 源极层，其形成在第二基极层的表面区域上，以与设置有第一栅电极的沟槽的两个侧壁相邻，并且设置有第二栅电极的沟槽的一个侧壁 ， 分别; 形成在第二表面上的第二导电类型的发射极层; 在第二基极层和源极层上形成的发射极; 在发射极层上形成的集电极; 以及分别电连接到第一和第二栅电极的第一和第二端子。
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公开(公告)号：US20050056912A1
公开(公告)日：2005-03-17
申请号：US10689608
申请日：2003-10-22
申请人： Hideaki Ninomiya , Tomoki Inoue
发明人： Hideaki Ninomiya , Tomoki Inoue
IPC分类号： H01L21/28 , H01L21/3205 , H01L23/52 , H01L29/06 , H01L29/40 , H01L29/41 , H01L29/861 , H01L29/76
CPC分类号： H01L29/404 , H01L29/0619 , H01L29/0692 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device disclosed herein comprises: a first base region which is of a first conductivity type; a second base region which is of a second conductivity type and which is selectively formed on a major surface of the first base region; a stopper region which is of a first conductivity type and which is formed on the major surface of the first base region, the stopper region being a predetermined distance away from the second base region and surrounding the second base region; and a ring region which is of a second conductivity type which is formed on the major surface of the first base region between the second base region and the stopper region, the ring region being spirally around the second base region and electrically connected to the second base region and the stopper region.
摘要翻译： 本文公开的半导体器件包括：第一导电类型的第一基极区; 第二基极区域，其具有第二导电类型并且选择性地形成在所述第一基极区域的主表面上; 阻挡区域，其具有第一导电类型并且形成在第一基底区域的主表面上，止挡区域距第二基底区域预定距离并且围绕第二基底区域; 以及形成在所述第二基极区域和所述阻挡区域之间的所述第一基底区域的主表面上的第二导电类型的环形区域，所述环形区域围绕所述第二基极区域螺旋地且与所述第二基底区域电连接 区域和止挡区域。
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公开(公告)号：US5523729A
公开(公告)日：1996-06-04
申请号：US190321
申请日：1993-11-19
申请人： Shinya Nakai , Hideaki Ninomiya , Hideaki Shimoda
发明人： Shinya Nakai , Hideaki Ninomiya , Hideaki Shimoda
CPC分类号： H01P1/20345 , H01P1/2056 , H03H7/09 , H03H7/1708 , H03H7/1775 , H03H2001/0085
摘要： A multilayer band pass filter includes a zero point forming capacitor formed by a plurality of capacitors connected in series between first and second extension electrodes, and intermediate capacitors connected between each pair of adjacent series capacitors and the open end of a core conductor. Therefore, zero points can be formed at the lower and upper limits of a given band. The capacity of these capacitors is adjustable via extension electrodes which extend outside the baked ceramic casing, thereby allowing adjustment to be made to the zero point.
摘要翻译： 多层带通滤波器包括由串联连接在第一和第二延伸电极之间的多个电容器和连接在每对相邻串联电容器和芯导体的开口端之间的中间电容器形成的零点形成电容器。 因此，可以在给定频带的下限和上限处形成零点。 这些电容器的容量可以通过延伸电极调节，延伸电极延伸到烘烤的陶瓷外壳的外部，从而允许调整到零点。
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公开(公告)号：US07845071B2
公开(公告)日：2010-12-07
申请号：US11072989
申请日：2005-03-07
IPC分类号： H05K3/30
CPC分类号： H01L31/18 , H01L21/67132 , H05K1/0393 , H05K3/0058 , Y10T29/49117 , Y10T29/4913 , Y10T29/49131 , Y10T29/49144 , Y10T29/5193 , Y10T29/53174
摘要： The present invention provides a substrate holding method capable of contributing to improvement in performance of an electronic part. A plastic film is adhered to a holding frame by using an adhesive tape having a proper gas releasing characteristic such that total quantity of gas detected when analysis using gas chromatograph mass spectrometry (dynamic HS-GC-MS) is conducted under test conditions of 180° C. and 10 minutes is 100.5 μg/g or less in n-tetradecane. In the case where the plastic film held by the holding frame is subjected to a process of manufacturing an electronic part (for example, a solar battery), even when a process accompanying generation of heat during the manufacturing process (for example, a film forming process such as plasma CVD) is performed on the plastic film, a release amount of unnecessary gas released from the adhesive tape due to the influence of the heat is suppressed, so that deterioration in the performance of the electronic part caused by the unnecessary gas is suppressed.
摘要翻译： 本发明提供能够有助于提高电子部件的性能的基板保持方法。 通过使用具有适当的气体释放特性的粘合带将塑料膜粘附到保持框架上，使得在使用气相色谱质谱（动态HS-GC-MS）进行分析时检测到的气体总量在180°的测试条件下进行 C.正十四烷中10分钟为100.5μg/ g以下。 在由保持框架保持的塑料膜经受制造电子部件（例如，太阳能电池）的处理的情况下，即使在制造过程中伴随发热的处理（例如，成膜 在塑料膜上进行等离子体CVD等工序），能够抑制由于热量的影响而从粘合带释放的不需要的气体的释放量，不利气体导致的电子部件的性能下降 被压制
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公开(公告)号：US07492031B2
公开(公告)日：2009-02-17
申请号：US11434185
申请日：2006-05-16
IPC分类号： H01L29/00
CPC分类号： H01L29/7397 , H01L29/4232 , H01L29/42372 , H01L29/7395
摘要： A semiconductor device comprises a first base layer of a first conductive type which has a first surface and a second surface; a second base layer of a second conductive type which is formed on the first surface; first and second gate electrodes which are formed by embedding an electrically conductive material into a plurality of trenches via gate insulating films, the plurality of trenches being formed such that bottoms of the trenches reach the first base layer; source layers of the first conductive type which are formed on a surface area of the second base layer so as to be adjacent to both side walls of the trench provided with the first gate electrode and one side wall of the trench provided with the second gate electrode, respectively; an emitter layer of the second conductive type which is formed on the second surface; emitter electrodes which are formed on the second base layer and the source layers; a collector electrode which is formed on the emitter layer; and first and second terminals which are electrically connected to the first and second gate electrodes, respectively.
摘要翻译： 半导体器件包括具有第一表面和第二表面的第一导电类型的第一基底层; 形成在第一表面上的第二导电类型的第二基层; 通过经由栅极绝缘膜将导电材料嵌入多个沟槽而形成的第一和第二栅电极，所述多个沟槽形成为使得沟槽的底部到达第一基底层; 源极层，其形成在第二基极层的表面区域上，以与设置有第一栅电极的沟槽的两个侧壁相邻，并且设置有第二栅电极的沟槽的一个侧壁 ， 分别; 形成在第二表面上的第二导电类型的发射极层; 在第二基极层和源极层上形成的发射极; 在发射极层上形成的集电极; 以及分别电连接到第一和第二栅电极的第一和第二端子。
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公开(公告)号：US20090039386A1
公开(公告)日：2009-02-12
申请号：US12249573
申请日：2008-10-10
IPC分类号： H01L29/739
CPC分类号： H01L29/1095 , H01L29/0834 , H01L29/7397
摘要： A semiconductor device comprises a first base layer of a first conductivity type; a plurality of second base layers of a second conductivity type, provided on a part of a first surface of the first base layer; trenches formed on each side of the second base layers, and formed to be deeper than the second base layers; an emitter layer formed along the trench on a surface of the second base layers; a collector layer of the second conductivity type, provided on a second surface of the first base layer opposite to the first surface; an insulating film formed on an inner wall of the trench, the insulating film being thicker on a bottom of the trench than on a side surface of the trench; a gate electrode formed within the trench, and isolated from the second base layers and the emitter layer by the insulating film; and a space section provided between the second base layers adjacent to each other, the space section being deeper than the second base layers and being electrically isolated from the emitter layer and the second base layers.
摘要翻译： 半导体器件包括第一导电类型的第一基极层; 多个第二导电类型的第二基层，设置在所述第一基底层的第一表面的一部分上; 沟槽形成在第二基底层的每一侧上，并且形成为比第二基底层更深; 在所述第二基底层的表面上沿着所述沟槽形成的发射极层; 设置在与第一表面相对的第一基底层的第二表面上的第二导电类型的集电极层; 形成在所述沟槽的内壁上的绝缘膜，所述绝缘膜在所述沟槽的底部比在所述沟槽的侧表面上更厚; 形成在所述沟槽内并与所述第二基极层和所述发射极层通过所述绝缘膜隔离的栅电极; 以及设置在彼此相邻的第二基底层之间的空间部分，空间部分比第二基底层更深，并且与发射极层和第二基底层电隔离。
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公开(公告)号：US07268390B2
公开(公告)日：2007-09-11
申请号：US11102851
申请日：2005-04-11
申请人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
发明人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
IPC分类号： H01L29/76
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/083 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.
摘要翻译： 半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到 阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层 形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。
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公开(公告)号：US20060006409A1
公开(公告)日：2006-01-12
申请号：US11221702
申请日：2005-09-09
IPC分类号： H01L29/423
CPC分类号： H01L29/0696 , H01L29/0619 , H01L29/0839 , H01L29/407 , H01L29/4236 , H01L29/66348 , H01L29/7394 , H01L29/7395 , H01L29/7397
摘要： A power semiconductor device includes trenches disposed in a first base layer of a first conductivity type at intervals to partition main and dummy cells, at a position remote from a collector layer of a second conductivity type. In the main cell, a second base layer of the second conductivity type, and an emitter layer of the first conductivity type are disposed. In the dummy cell, a buffer layer of the second conductivity type is disposed. A gate electrode is disposed, through a gate insulating film, in a trench adjacent to the main cell. A buffer resistor having an infinitely large resistance value is inserted between the buffer layer and emitter electrode. The dummy cell is provided with an inhibiting structure to reduce carriers of the second conductivity type to flow to and accumulate in the buffer layer from the collector layer.
摘要翻译： 功率半导体器件包括在距离第二导电类型的集电极层的位置处间隔设置在第一导电类型的第一基极层中的沟槽，以分隔主单元和虚设单元。 在主电池中，设置第二导电类型的第二基极层和第一导电类型的发射极层。 在虚拟电池中设置第二导电类型的缓冲层。 栅电极通过栅极绝缘膜设置在与主电池相邻的沟槽中。 具有无限大电阻值的缓冲电阻器插入在缓冲层和发射极之间。 虚设电池具有抑制结构，以减少第二导电类型的载流子从集电极层流入和积聚在缓冲层中。
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公开(公告)号：US20050179083A1
公开(公告)日：2005-08-18
申请号：US11102851
申请日：2005-04-11
申请人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
发明人： Tsuneo Ogura , Tomoki Inoue , Hideaki Ninomiya , Koichi Sugiyama
IPC分类号： H01L29/78 , H01L21/8228 , H01L29/06 , H01L29/10 , H01L29/739 , H01L29/76 , H01L29/94 , H01L31/0328 , H01L31/0336 , H01L31/062 , H01L31/072 , H01L31/109
CPC分类号： H01L29/1095 , H01L29/0619 , H01L29/0692 , H01L29/0696 , H01L29/083 , H01L29/0834 , H01L29/7394 , H01L29/7397
摘要： A semiconductor device includes a base layer of a first conductivity type, a barrier layer of a first conductivity type formed on the base layer, a trench formed from the surface of the barrier layer to such a depth as to reach a region in the vicinity of an interface between the barrier layer and the base layer, a gate electrode formed in the trench via a gate insulating film, a contact layer of a second conductivity type selectively formed in a surface portion of the barrier layer, a source layer of the first conductivity type selectively formed in the surface portion of the barrier layer so as to contact the contact layer and a side wall of the gate insulating film in the trench, and a first main electrode formed so as to contact the contact layer and the source layer.
摘要翻译： 半导体器件包括第一导电类型的基底层，形成在基底层上的第一导电类型的阻挡层，从阻挡层的表面形成的沟槽到达达到 阻挡层和基底层之间的界面，通过栅极绝缘膜形成在沟槽中的栅极电极，选择性地形成在阻挡层的表面部分中的第二导电类型的接触层，第一导电性的源极层 形成在所述阻挡层的表面部分中以与所述沟槽中的所述接触层和所述栅极绝缘膜的侧壁接触的第一主电极以及与所述接触层和所述源极层接触的第一主电极。
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公开(公告)号：US06534998B1
公开(公告)日：2003-03-18
申请号：US09716381
申请日：2000-11-21
IPC分类号： G01R3108
CPC分类号： H01L29/7395 , H03K17/08128
摘要： Disclosed is a semiconductor device capable of stabilizing a gate voltage at high voltage and high current, protecting the device from breakdown by preventing current nonuniformity and oscillations and the like, thereby improving reliability, and a method for controlling the semiconductor device. The semiconductor device comprises an n-type base layer, a p-type emitter layer, which is formed on a surface of the n-type base layer, a collector electrode, formed on a surface of the p-type emitter layer, a p-type base layer, formed on a surface on the n-type base layer which is opposite to the p-type emitter layer, an n-type source layer, formed in a surface of the p-type base layer, an emitter electrode, formed on the n-type source layer and the p-type base layer, and a gate electrode, contacting the n-type source layer, the p-type base layer and the n-type base layer, with a gate insulating film interposed therebetween, wherein when a voltage is applied between the collector electrode and the emitter electrode, the capacitance of the gate electrode is always a positive value or zero.
摘要翻译： 公开了一种能够在高电压和高电流下稳定栅极电压的半导体器件，通过防止电流不均匀性和振荡等来保护器件免于击穿，从而提高可靠性，以及用于控制半导体器件的方法。 半导体器件包括n型基极层，形成在n型基极层的表面上的p型发射极层，形成在p型发射极层的表面上的集电极，p 型基底层，形成在与p型发射极层相对的n型基底层的表面上，形成在p型基底层的表面中的n型源极层，发射极电极， 形成在n型源极层和p型基极层上的栅极电极和与n型源极层，p型基极层和n型基极层接触的栅极电极，其间插入有栅极绝缘膜 其中当在集电极和发射极之间施加电压时，栅电极的电容总是为正值或零。
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