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122 条记录 (耗时 0.058 秒)

    Nonvolatile semiconductor memory device
    11.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5949715A

    公开(公告)日：1999-09-07

    申请号：US720007

    申请日：1996-09-27

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Nonvolatile semiconductor memory device
    14.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US06259629B1

    公开(公告)日：2001-07-10

    申请号：US09425041

    申请日：1999-10-19

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C1134

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Nonvolatile semiconductor memory device
    15.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06181600B2

    公开(公告)日：2001-01-30

    申请号：US09342225

    申请日：1999-06-29

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C1134

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    摘要翻译： 在具有其中电可擦除非易失性存储元件以矩阵形式布置的存储器阵列的EEPROM中，包括擦除控制电路，其在执行擦除操作之后在对应的存储器单元上至少执行一次读出操作 根据外部提供的擦除操作指令。 擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。 微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。 在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反的极性的擦除电压施加到控制栅极 电极。 擦除电压被提供给设置在非易失性存储器件内的电压转换电路。 因此，可以通过Vcc单电源实现擦除操作。 此外，响应于每个存储元件的单独擦除速度，对于每个存储元件或每个集合存储元件单独控制集体擦除操作的实质端子。

    Nonvolatile semiconductor memory device
    16.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US6016273A

    公开(公告)日：2000-01-18

    申请号：US720060

    申请日：1996-09-27

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Nonvolatile semiconductor memory device
    17.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5959894A

    公开(公告)日：1999-09-28

    申请号：US98747

    申请日：1998-06-17

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks
    19.
    发明授权
    Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks 失效
    具有划分为存储块的存储单元阵列的电可擦除半导体非易失性存储器件

    公开(公告)号：US06288941B1

    公开(公告)日：2001-09-11

    申请号：US08379020

    申请日：1995-01-27

    申请人： Kouichi Seki ,  Toshihiro Tanaka ,  Hitoshi Kume ,  Takeshi Wada ,  Tadashi Muto

    发明人： Kouichi Seki ,  Toshihiro Tanaka ,  Hitoshi Kume ,  Takeshi Wada ,  Tadashi Muto

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C8/12 ,  G11C16/16

    摘要： An electrically erasable semiconductor nonvolatile memory device has an array of memory cells arranged in rows and columns and one or more information erasure signal generating circuits. Each of the memory cells of the memory cell array includes a field-effect transistor element having a control gate connected with a word line conductor extending in a direction of the rows, a floating gate where carriers may be accumulated, a drain connected with a data line conductor extending in the direction of the columns and a source connected with a source conductor. The memory cell array may be divided into a plurality of memory blocks so as to have boundaries in the row direction or in the column direction, with the source conductors arranged in the row direction or in the column direction. Information erasure signals may be supplied to the source conductors or data line conductors with a time delay therebetween.

    摘要翻译： 电可擦除半导体非易失性存储器件具有排列成行和列的存储单元阵列和一个或多个信息擦除信号发生电路。 存储单元阵列的每个存储单元包括场效应晶体管元件，其具有与沿着行的方向延伸的字线导体连接的控制栅极，可以累积载流子的浮置栅极，与数据相连的漏极 线导体沿列的方向延伸，源极与源极连接。 存储单元阵列可以被划分为多个存储块，以便在行方向或列方向上具有沿着行方向或列方向布置的源极的边界。 信息擦除信号可以以它们之间的时间延迟提供给源极导体或数据线导体。