公开(公告)号：US4996571A

公开(公告)日：1991-02-26

申请号：US375956

申请日：1989-07-06

申请人： Hitoshi Kume ,  Yoshiaki Kamigaki ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Kazuhiro Komori ,  Toshiaki Nishimoto ,  Tadashi Muto ,  Toshiko Koizumi

发明人： Hitoshi Kume ,  Yoshiaki Kamigaki ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Kazuhiro Komori ,  Toshiaki Nishimoto ,  Tadashi Muto ,  Toshiko Koizumi

IPC分类号： G11C17/00 ,  G11C16/04 ,  G11C16/14 ,  H01L29/788

CPC分类号： G11C16/3477 ,  G11C16/14 ,  H01L29/7884

摘要： The invention relates to a tunnel erasing device for a non-volatile semiconductor memory device comprising a source region and a drain region, a floating gate electrode having a part superposed on at least one of them through a gate insulating layer, and a control gate electrode disposed over the floating gate electrode through an interlayer insulating layer and is characterized as having a preliminary erasing operation in which a voltage is so applied to at least one of the source or drain region, with the control gate electrode grounded, that a relatively lower voltage than a predetermined voltage is applied preliminarily prior to applying thereto the predetermined voltage.

摘要翻译： 本发明涉及一种用于非易失性半导体存储器件的隧道擦除装置，包括源极区和漏极区，通过栅极绝缘层将具有重叠在其中的至少一个上的部分的浮栅电极和控制栅电极 通过层间绝缘层设置在浮栅上，并且其特征在于具有预先擦除操作，其中电压被施加到源区或漏区中的至少一个，控制栅电极接地，相对较低的电压 预先施加预定电压之前施加预定电压。

公开(公告)号：US4972371A

公开(公告)日：1990-11-20

申请号：US203456

申请日：1988-06-07

申请人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

发明人： Kazuhiro Komori ,  Takaaki Hagiwara ,  Satoshi Meguro ,  Toshiaki Nishimoto ,  Takeshi Wada ,  Kiyofumi Uchibori ,  Tadashi Muto ,  Hitoshi Kume ,  Hideaki Yamamoto ,  Tetsuo Adachi ,  Toshihisa Tsukada ,  Toshiko Koizumi

IPC分类号： G11C16/04 ,  H01L27/115 ,  H01L29/788

CPC分类号： G11C16/0416 ,  H01L27/115 ,  H01L29/7884

摘要： An EEPROM in which a memory cell is constituted by a floating gate electrode, a control gate electrode, a first semiconductor region provided in a main surface portion of the semiconductor substrate on an end side of the gate electrodes to which the data line is connected, and a second semiconductor region provided in a different main surface portion of the semiconductor substrate on an opposing end side of the gate electrodes to which the grounding line is connected. The drain is used differently depending upon the operations for writing the data, reading the data and erasing the data. The impurity concentration in the first semiconductor region is selected to be lower than that of the second semiconductor region, in order to improve writing and erasing characteristics as well as to increase the reading speed.

摘要翻译： 一种EEPROM，其中存储单元由浮置栅电极，控制栅极电极，设置在半导体衬底的主表面部分中的与数据线连接的栅电极的端侧上的第一半导体区域构成， 以及第二半导体区域，设置在与所述接地线连接的所述栅电极的相对端侧的所述半导体衬底的不同主表面部分中。 漏极的使用方式取决于写入数据的操作，读取数据和擦除数据。 选择第一半导体区域中的杂质浓度低于第二半导体区域的杂质浓度，以提高写入和擦除特性以及增加读取速度。

公开(公告)号：US20080219082A1

公开(公告)日：2008-09-11

申请号：US12046150

申请日：2008-03-11

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C8/06 ,  G11C8/10

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

摘要翻译： 公开了一种非易失性存储器系统，包括至少一个非易失性存储器，每个非易失性存储器具有多个非易失性存储单元和缓冲存储器; 以及耦合到所述非易失性存储器的控制装置。 控制装置能够接收外部数据并将数据应用于非易失性存储器，并且使非易失性存储器能够操作程序操作，包括将接收到的数据存储到缓冲存储器并将保存在缓冲存储器中的数据存储到缓冲存储器中 的非易失性存储单元。 此外，控制装置能够在非易失性存储器在程序操作中操作时接收外部数据。 此外，缓冲存储器能够接收与程序运行一次要存储的数据的数据长度相等的数据单位，数据长度大于1字节。

公开(公告)号：US06738310B2

公开(公告)日：2004-05-18

申请号：US10351524

申请日：2003-01-27

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C700

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Disclosed is a nonvolatile memory system including at least one nonvolatile memory each having a plurality of nonvolatile memory cells and a buffer memory; and a control device coupled to the nonvolatile memory. The control device is enabled to receive external data and to apply the data to the nonvolatile memory, and the nonvolatile memory is enabled to operate a program operation including storing the received data to the buffer memory and storing the data held in the buffer memory to ones of nonvolatile memory cells. Moreover, the control device is enabled to receive external data while the nonvolatile memory is operating in the program operation. Also, the buffer memory is capable of receiving a unit of data, equal to the data length of data to be stored at one time of the program operation, the data length being more than 1 byte.

公开(公告)号：US06272042B1

公开(公告)日：2001-08-07

申请号：US09630426

申请日：2000-08-01

申请人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

发明人： Masataka Kato ,  Tetsuo Adachi ,  Toshihiro Tanaka ,  Toshio Sasaki ,  Hitoshi Kume ,  Katsutaka Kimura

IPC分类号： G11C1604

CPC分类号： G11C16/0416 ,  G11C8/08 ,  G11C16/10 ,  G11C16/12 ,  G11C16/16 ,  G11C16/34 ,  G11C16/3418 ,  G11C16/3427 ,  H01L27/115 ,  H01L27/11521 ,  H01L27/11524 ,  H01L29/7883 ,  H01L29/7885

摘要： Each memory cell of a nonvolatile semiconductor memory, essentially, consists of a one-transistor type memory cell such as a MOSFET having a floating gate electrode. When an electric programming operation is carried out, a positive voltage is applied to an n type drain region, a negative voltage is applied to a control gate and a source region is grounded. When an erasing operation is carried out, the positive voltage is applied to the control gate while all the other electrodes and a semiconductor substrate are grounded. Low power consumption can be accomplished because both of the programming operation and erasing operations are carried out by utilizing a tunneling mechanism. Furthermore, because the negative voltage applied to the word line, a drain voltage at the time of programming of data can be lowered, so that degradation of a gate oxide film at a channel portion can be mitigated.

摘要翻译： 非易失性半导体存储器的每个存储单元基本上由诸如具有浮置栅电极的MOSFET的单晶体管型存储单元组成。 当执行电编程操作时，向n型漏极区域施加正电压，向控制栅极施加负电压，并且源极区域接地。 当执行擦除操作时，正电压被施加到控制栅极，而所有其它电极和半导体衬底接地。 可以实现低功耗，因为通过利用隧道机制来执行编程操作和擦除操作两者。 此外，由于施加到字线的负电压，可以降低数据编程时的漏极电压，从而可以减轻沟道部分处的栅极氧化膜的劣化。

公开(公告)号：US5793678A

公开(公告)日：1998-08-11

申请号：US628817

申请日：1996-04-05

申请人： Masataka Kato ,  Tetsuo Adachi ,  Hitoshi Kume ,  Takashi Kobayashi

发明人： Masataka Kato ,  Tetsuo Adachi ,  Hitoshi Kume ,  Takashi Kobayashi

IPC分类号： G11C17/00 ,  G11C5/14 ,  G11C16/04 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C16/16 ,  H01L21/8246 ,  H01L21/8247 ,  H01L27/112 ,  H01L27/115 ,  H01L29/788 ,  H01L29/792

CPC分类号： G11C16/16 ,  G11C16/0416 ,  G11C16/10 ,  G11C16/12 ,  G11C16/14 ,  G11C5/146 ,  H01L27/115

摘要： On a semiconductor substrate of a first conductive type is formed a well layer of the same conductive type as that of the substrate in electrically separated that is, physically separated and electrically isolated, from the substrate, and a MOS transistor, used as a nonvolatile memory cell, forming a drain region and a source region respectively within the well layer is used as a memory cell. Well layers associated with different columns are connected to each other by a well wiring commonly so that operation voltage different from that of the semiconductor substrate is applied thereto. In the case of data erasing, prescribed positive voltage is applied to a well wiring, and prescribed voltage lower than said positive voltage is applied to a selected word line. In the case of data programming, prescribed negative voltage is applied to the well wiring, prescribed voltage higher than said negative voltage is applied to the selected word line.

摘要翻译： 在第一导电类型的半导体衬底上形成与基板电性分离的物理层相同的导电类型的阱层，该衬底与衬底物理分离和电绝缘，以及用作非易失性存储器的MOS晶体管 在阱层内分别形成漏极区域和源极区域的单元被用作存储单元。 与不同列相关联的阱层通常通过阱布线彼此连接，使得与半导体衬底的操作电压不同。 在数据擦除的情况下，将规定的正电压施加到阱布线，并且将低于所述正电压的规定电压施加到所选择的字线。 在数据编程的情况下，将规定的负电压施加到阱布线，将高于所述负电压的规定电压施加到所选择的字线。

公开(公告)号：US07692234B2

公开(公告)日：2010-04-06

申请号：US11862928

申请日：2007-09-27

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US07528036B2

公开(公告)日：2009-05-05

申请号：US11107826

申请日：2005-04-18

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/336

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

公开(公告)号：US07304345B2

公开(公告)日：2007-12-04

申请号：US11266430

申请日：2005-11-04

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L29/788

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.

摘要翻译： 一种半导体器件，其特别是确保器件的可靠性，特别是在微细的区域中并且能够实现大的电容和高速操作，具有在半导体衬底的主表面的第一区域中包括栅绝缘膜，浮栅电极， 层间绝缘膜，控制栅极电极以及以矩阵形式布置的第二导电类型的源极和漏极区域，具有用于隔离存储单元的浅隔离结构。 当使用用绝缘膜掩埋的浅结构用于元件隔离时，可以防止微细区域中的隔离耐受电压降低，并且可以降低选择性晶体管的阈值电平的变化。 当通过选择性晶体管分配存储器垫中的存储单元时，可以提高存储单元的干扰电阻。

公开(公告)号：US07141475B2

公开(公告)日：2006-11-28

申请号：US10954102

申请日：2004-09-30

申请人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

发明人： Tetsuo Adachi ,  Masataka Kato ,  Toshiaki Nishimoto ,  Nozomu Matsuzaki ,  Takashi Kobayashi ,  Yoshimi Sudou ,  Toshiyuki Mine

IPC分类号： H01L21/8247

CPC分类号： H01L21/28273 ,  G11C11/5628 ,  G11C16/0466 ,  G11C16/10 ,  G11C16/3454 ,  H01L21/28061 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11519 ,  H01L27/11526 ,  H01L27/11529 ,  H01L27/11536 ,  H01L27/11546 ,  H01L29/6659 ,  H01L29/66825 ,  H01L29/7833

摘要： A semiconductor device, which ensures device reliability especially in fine regions and enables great capacitance and high-speed operations, has memory cells including, in a first region of a main surface of a semiconductor substrate, a gate insulating film, a floating gate electrode, an interlayer insulating film, a control gate electrode, and source and drain regions of the second conduction type arranged in a matrix, with a shallow isolation structure for isolating the memory cells. When using a shallow structure buried with an insulating film for element isolation, the isolation withstand voltage in fine regions can be prevented from lowering and the variation in threshold level of selective transistors can be reduced. When the memory cells in a memory mat are divided by means of selective transistors, the disturb resistance of the memory cells can be improved.