利索-全球专利检索

  1. 登录
  2. 注册

搜索结果

161 条记录 (耗时 0.053 秒)

    Nonvolatile semiconductor memory device
    12.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US07099199B2

    公开(公告)日：2006-08-29

    申请号：US10837593

    申请日：2004-05-04

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C11/34 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： A nonvolatile memory apparatus which includes plural memories one of which is a nonvolatile memory such as a Flash EEPROM capable of being specified a plurality of operations from a processing unit of the apparatus including an erase operation, the erase operation in the nonvolatile memory performs a threshold voltage moving operation and a verify operation, and the nonvolatile memory is capable of releasing the I/O bus during the erase operation to thereby allow accessing of other memories and/or system components. For example, during this erase operation, the Flash EEPROM is able to free the I/O data terminal such that the EEPROM becomes electrically isolated from the CPU. The CPU is then able to perform data processing by the system bus where information can then be transferred/received such as between other memories, e.g., ROM and RAM, and otherwise with the I/O port.

    摘要翻译： 一种非易失性存储装置，包括多个存储器，其中一个是诸如闪存EEPROM的非易失性存储器，其能够从包括擦除操作的装置的处理单元指定多个操作，所述非易失性存储器中的擦除操作执行阈值 电压移动操作和验证操作，并且非易失性存储器能够在擦除操作期间释放I / O总线，从而允许访问其他存储器和/或系统组件。 例如，在擦除操作期间，闪存EEPROM能够释放I / O数据终端，使得EEPROM与CPU电隔离。 CPU然后能够执行系统总线的数据处理，其中可以在诸如ROM和RAM等其他存储器之间传输/接收信息，否则可以与I / O端口进行数据处理。

    Nonvolatile semiconductor memory device
    13.
    发明授权
    Nonvolatile semiconductor memory device 失效
    非易失性半导体存储器件

    公开(公告)号：US06791882B2

    公开(公告)日：2004-09-14

    申请号：US10175958

    申请日：2002-06-21

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C1604

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： An EEPROM having an erasing control circuit that performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the disclosure, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode.

    摘要翻译： 一种具有擦除控制电路的EEPROM，该擦除控制电路在与之相关的擦除操作之后至少对相应的存储单元执行一次读出操作。 擦除操作由内部擦除控制电路自动执行，同时响应于来自微处理器的指令，EEPROM与微处理器电隔离。 微处理器的控制只需要稍微短的时间段，在擦除操作期间EEPROM保留在系统中时，指令擦除开始。 在本发明的一个方面中，将Vcc电源施加到每个非易失性半导体存储单元的源极区域或漏极区域，并且将具有与Vcc电源的极性相反极性的擦除电压施加到控制栅电极 。

    Nonvolatile semiconductor memory device
    14.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5991200A

    公开(公告)日：1999-11-23

    申请号：US470212

    申请日：1995-06-06

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C16/04

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Nonvolatile semiconductor memory device
    15.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5949715A

    公开(公告)日：1999-09-07

    申请号：US720007

    申请日：1996-09-27

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Nonvolatile semiconductor memory device
    17.
    发明授权
    Nonvolatile semiconductor memory device 失效

    公开(公告)号：US5917752A

    公开(公告)日：1999-06-29

    申请号：US457761

    申请日：1995-06-01

    申请人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    发明人： Koichi Seki ,  Takeshi Wada ,  Tadashi Muto ,  Kazuyoshi Shoji ,  Yasurou Kubota ,  Hitoshi Kume

    IPC分类号： G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/34 ,  G11C11/34

    CPC分类号： G11C16/3445 ,  G11C16/06 ,  G11C16/12 ,  G11C16/16 ,  G11C16/30 ,  G11C16/32 ,  G11C16/344 ,  G11C2216/20

    摘要： Within an EEPROM having a memory array in which the electrically erasable nonvolatile storage elements are arranged in a matrix form, an erasing control circuit is included, which performs at least the read out operation one time on the corresponding memory cells after an erasing operation is performed in connection therewith in accordance with externally supplied erasing operation instructions. The erasing operation is automatically performed by the internal erasing control circuit while the EEPROM is electrically isolated from the microprocessor in response to instructions from the microprocessor. The control by the microprocessor requires only a slightly short period of time during which the erasing commencement is instructed while the EEPROM remains in the system during the erasing operation. In one aspect of the present invention, a Vcc power source is applied to a source region or a drain region of each nonvolatile semiconductor memory cell, and an erasure voltage having a polarity opposite to that of the Vcc power source is applied to a control gate electrode. The erasure voltage is supplied to a voltage conversion circuit provided within the nonvolatile memory device. Accordingly, erasure operation can be realized by the Vcc single power source. Further, substantial terminals of the collective erasure operation are individually controlled for every memory element or every collective memory element in response to the individual erasure speed of each memory element.

    Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks
    19.
    发明授权
    Electrically erasable semiconductor non-volatile memory device having memory cell array divided into memory blocks 失效
    具有划分为存储块的存储单元阵列的电可擦除半导体非易失性存储器件

    公开(公告)号：US06288941B1

    公开(公告)日：2001-09-11

    申请号：US08379020

    申请日：1995-01-27

    申请人： Kouichi Seki ,  Toshihiro Tanaka ,  Hitoshi Kume ,  Takeshi Wada ,  Tadashi Muto

    发明人： Kouichi Seki ,  Toshihiro Tanaka ,  Hitoshi Kume ,  Takeshi Wada ,  Tadashi Muto

    IPC分类号： G11C1604

    CPC分类号： G11C16/10 ,  G11C8/12 ,  G11C16/16

    摘要： An electrically erasable semiconductor nonvolatile memory device has an array of memory cells arranged in rows and columns and one or more information erasure signal generating circuits. Each of the memory cells of the memory cell array includes a field-effect transistor element having a control gate connected with a word line conductor extending in a direction of the rows, a floating gate where carriers may be accumulated, a drain connected with a data line conductor extending in the direction of the columns and a source connected with a source conductor. The memory cell array may be divided into a plurality of memory blocks so as to have boundaries in the row direction or in the column direction, with the source conductors arranged in the row direction or in the column direction. Information erasure signals may be supplied to the source conductors or data line conductors with a time delay therebetween.

    摘要翻译： 电可擦除半导体非易失性存储器件具有排列成行和列的存储单元阵列和一个或多个信息擦除信号发生电路。 存储单元阵列的每个存储单元包括场效应晶体管元件，其具有与沿着行的方向延伸的字线导体连接的控制栅极，可以累积载流子的浮置栅极，与数据相连的漏极 线导体沿列的方向延伸，源极与源极连接。 存储单元阵列可以被划分为多个存储块，以便在行方向或列方向上具有沿着行方向或列方向布置的源极的边界。 信息擦除信号可以以它们之间的时间延迟提供给源极导体或数据线导体。

    Metal member manufacturing method and metal member
    20.
    发明授权
    Metal member manufacturing method and metal member 有权
    金属构件制造方法和金属构件

    公开(公告)号：US09279186B2

    公开(公告)日：2016-03-08

    申请号：US13574854

    申请日：2010-10-22

    申请人： Hidemi Kato ,  Takeshi Wada ,  Kunio Yubuta ,  Akihisa Inoue

    发明人： Hidemi Kato ,  Takeshi Wada ,  Kunio Yubuta ,  Akihisa Inoue

    IPC分类号： C23F4/04 ,  C23C26/02 ,  C23F1/00 ,  C22B9/02 ,  C22B26/22

    CPC分类号： C23C26/02 ,  B22F2998/00 ,  C22B9/02 ,  C22B26/22 ,  C23F1/00 ,  C23F4/04 ,  Y02P10/234 ,  Y10T428/12479 ,  C22C1/0425 ,  C22C1/0433 ,  C22C33/02

    摘要： A metallic material containing both a second constituent and a third constituent having positive and negative heats of mixing relative to a first constituent, respectively, and including a compound, an alloy or a nonequilibrium alloy having a melting point that is higher than the solidifying point of a metal bath made of the first constituent is placed in the metal bath. The metal bath is controlled to a temperature lower than a minimum value of a liquidus temperature within a range of compositional variations in which the amount of the third constituent in the metallic material decreases down to a point where the metallic material becomes substantially the second constituent so that the third constituent is selectively dissolved into the metal bath.

    摘要翻译： 一种含有第二成分和第三成分的金属材料，分别具有相对于第一成分的正和负的混合热，并且包括熔点高于凝固点的化合物，合金或非平衡合金 将由第一成分制成的金属浴放置在金属浴中。 将金属浴控制在低于液相线温度的最小值的温度范围内，其中金属材料中的第三成分的量减少到金属材料基本上变成第二成分的程度 第三组分选择性地溶解到金属浴中。