公开(公告)号：US20110248332A1

公开(公告)日：2011-10-13

申请号：US13007533

申请日：2011-01-14

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L29/792 ,  H01L21/3205

CPC classification number: H01L29/512 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3145 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

Abstract translation: 提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。 通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氮氧化物层上的贫氧的第二氧氮化物层 第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。 还公开了其他实施例。

公开(公告)号：US20070184597A1

公开(公告)日：2007-08-09

申请号：US11350160

申请日：2006-02-07

Applicant: Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Levy

Inventor： Igor Polishchuk ,  Krishnaswamy Ramkumar ,  Sagy Levy

IPC: H01L21/8234

CPC classification number: H01L21/823807 ,  H01L21/823864 ,  H01L29/7843

Abstract: In one embodiment, a self-aligned contact (SAC) trench structure is formed through a dielectric layer to expose an active region of a MOS transistor. The SAC trench structure not only exposes the active region for electrical connection but also removes portions of a stress liner over the active region. This leaves the stress liner mostly on the sidewall and top of the gate of the MOS transistor. Removing portions of the stress liner over the active region substantially removes the lateral component of the strain imparted by the stress liner on the substrate, allowing for improved drive current without substantially degrading a complementary MOS transistor.

Abstract translation: 在一个实施例中，通过电介质层形成自对准接触（SAC）沟槽结构以暴露MOS晶体管的有源区。 SAC沟槽结构不仅暴露用于电连接的有源区，而且还去除了有源区上的应力衬垫的部分。 这使得应力衬垫主要在MOS晶体管的侧壁和顶部上方。 在有源区上去除应力衬垫的部分基本上消除了由衬底上的应力衬垫施加的应变的横向分量，从而允许改进的驱动电流而不会使互补MOS晶体管基本上降级。

公开(公告)号：US08993453B1

公开(公告)日：2015-03-31

申请号：US13620071

申请日：2012-09-14

Applicant: Krishnaswamy Ramkumar ,  Jeong Byun ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Jeong Byun ,  Sagy Levy

IPC: H01L21/31

CPC classification number: H01L21/28282 ,  H01L21/3144 ,  H01L21/3145 ,  H01L29/4234 ,  H01L29/66833

Abstract: A method for fabricating a nonvolatile charge trap memory device and the device are described. In one embodiment, the method includes providing a substrate in an oxidation chamber, wherein the substrate comprises a first exposed crystal plane and a second exposed crystal plane, and wherein the crystal orientation of the first exposed crystal plane is different from the crystal orientation of the second exposed crystal plane. The substrate is then subjected to a radical oxidation process to form a first portion of a dielectric layer on the first exposed crystal plane and a second portion of the dielectric layer on the second exposed crystal plane, wherein the thickness of the first portion of the dielectric layer is approximately equal to the thickness of the second portion of the dielectric layer.

Abstract translation: 描述了一种用于制造非易失性电荷陷阱存储器件及其装置的方法。 在一个实施例中，该方法包括在氧化室中提供衬底，其中衬底包括第一暴露的晶体面和第二暴露的晶面，并且其中第一暴露的晶面的晶体取向不同于 第二次暴露的晶面。 然后对基板进行自由基氧化处理，以在第一暴露的晶面上形成电介质层的第一部分，在第二暴露的晶面上形成电介质层的第二部分，其中电介质的第一部分的厚度 层大致等于电介质层的第二部分的厚度。

公开(公告)号：US08871595B2

公开(公告)日：2014-10-28

申请号：US13436878

申请日：2012-03-31

Applicant: Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

Inventor： Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sagy Levy

IPC: H01L21/8239

CPC classification number: H01L29/7833 ,  B82Y10/00 ,  H01L21/28282 ,  H01L21/823412 ,  H01L21/823425 ,  H01L21/823462 ,  H01L27/105 ,  H01L27/1052 ,  H01L27/11568 ,  H01L27/11573 ,  H01L27/11582 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66833 ,  H01L29/7836 ,  H01L29/7843 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a method of integrating a non-volatile memory device into a logic MOS flow is described. Generally, the method includes: forming in a first region of a substrate a channel of a memory device from a semiconducting material overlying a surface of the substrate, the channel connecting a source and a drain of the memory device; forming a charge trapping dielectric stack over the channel adjacent to a plurality of surfaces of the channel, wherein the charge trapping dielectric stack includes a blocking layer on a charge trapping layer over a tunneling layer; and forming a MOS device over a second region of the substrate.

Abstract translation: 描述了将非易失性存储器件集成到逻辑MOS流中的方法的实施例。 通常，该方法包括：在衬底的第一区域中形成存储器件的通道，覆盖衬底表面的半导体材料，连接存储器件的源极和漏极的沟道; 在与所述通道的多个表面相邻的所述通道上形成电荷捕获电介质堆叠，其中所述电荷捕获电介质堆叠包括在隧道层上的电荷捕获层上的阻挡层; 以及在所述衬底的第二区域上形成MOS器件。

公开(公告)号：US08643124B2

公开(公告)日：2014-02-04

申请号：US13007533

申请日：2011-01-14

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick Jenne ,  Sam Geha

IPC: H01L21/336

CPC classification number: H01L29/512 ,  C23C16/0272 ,  C23C16/308 ,  G11C16/0466 ,  H01L21/0214 ,  H01L21/02271 ,  H01L21/28282 ,  H01L21/3145 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/7833 ,  H01L29/792

Abstract: A semiconductor device including a silicon-oxide-oxynitride-oxide-silicon structure and methods of forming the same are provided. Generally, the structure comprises: a tunnel oxide layer on a surface of a substrate including silicon; a multi-layer charge storing layer including an oxygen-rich, first oxynitride layer on the tunnel oxide layer in which the stoichiometric composition of the first oxynitride layer results in it being substantially trap free, and an oxygen-lean, second oxynitride layer on the first oxynitride layer in which the stoichiometric composition of the second oxynitride layer results in it being trap dense; a blocking oxide layer on the second oxynitride layer; and a silicon containing gate layer on the blocking oxide layer. Other embodiments are also disclosed.

Abstract translation: 提供了包括氧化硅 - 氧氮化物 - 氧化物 - 硅结构的半导体器件及其形成方法。 通常，该结构包括：在包括硅的衬底的表面上的隧道氧化物层; 多层电荷存储层，其包括在所述隧道氧化物层上的富氧第一氧氮化物层，其中所述第一氧氮化物层的化学计量组成导致其基本上不含杂质，并且所述第二氧氮化物层 第一氮氧化物层，其中第二氮氧化物层的化学计量组成导致其陷阱致密; 在第二氮氧化物层上的阻挡氧化物层; 以及在所述阻挡氧化物层上的含硅栅极层。 还公开了其他实施例。

公开(公告)号：US08592891B1

公开(公告)日：2013-11-26

申请号：US13539463

申请日：2012-07-01

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Byun

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar ,  Jeong Byun

IPC: H01L29/76

CPC classification number: H01L29/4234 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/792

Abstract: A semiconductor device and method of fabricating the same are provided. In one embodiment, the semiconductor device includes a memory transistor with an oxide-nitride-nitride-oxide (ONNO) stack disposed above a channel region. The ONNO stack comprises a tunnel dielectric layer disposed above the channel region, a multi-layer charge-trapping region disposed above the tunnel dielectric layer, and a blocking dielectric layer disposed above the multi-layer charge-trapping region. The multi-layer charge-trapping region includes a substantially trap-free layer comprising an oxygen-rich nitride and a trap-dense layer disposed above the trap-free layer. The semiconductor device further includes a strain inducing structure including a strain inducing layer disposed proximal to the ONNO stack to increase charge retention of the multi-layer charge-trapping region. Other embodiments are also disclosed.

Abstract translation: 提供了半导体器件及其制造方法。 在一个实施例中，半导体器件包括具有设置在沟道区上方的氧化氮化物 - 氮化物 - 氧化物（ONNO）堆的存储晶体管。 ONNO堆叠包括设置在沟道区上方的隧道介电层，设置在隧道介电层上方的多层电荷捕获区，以及设置在多层电荷俘获区上方的阻挡介质层。 多层电荷捕获区域包括基本上无陷阱层，其包含富含氧的氮化物和设置在无阱层之上的陷阱致密层。 半导体器件还包括应变诱导结构，其包括设置在ONNO堆叠附近的应变诱导层，以增加多层电荷俘获区域的电荷保留。 还公开了其他实施例。

公开(公告)号：US20090032863A1

公开(公告)日：2009-02-05

申请号：US12005813

申请日：2007-12-27

Applicant: Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

Inventor： Sagy Levy ,  Krishnaswamy Ramkumar ,  Fredrick B. Jenne

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L21/3143 ,  H01L29/4234 ,  H01L29/4916 ,  H01L29/512 ,  H01L29/513 ,  H01L29/518

Abstract: A method for forming a tunneling layer of a nonvolatile trapped-charge memory device and the article made thereby. The method includes multiple oxidation and nitridation operations to provide a dielectric constant higher than that of a pure silicon dioxide tunneling layer but with a fewer hydrogen and nitrogen traps than a tunneling layer having nitrogen at the substrate interface. The method provides for an improved memory window in a SONOS-type device. In one embodiment, the method includes an oxidation, a nitridation, a reoxidation and a renitridation. In one implementation, the first oxidation is performed with O2 and the reoxidation is performed with NO.

Abstract translation: 一种用于形成非易失性俘获电荷存储装置的隧道层的方法及其制成的制品。 该方法包括多次氧化和氮化操作，以提供比纯二氧化硅隧道层更高的介电常数，但是具有比在衬底界面处具有氮的隧穿层更少的氢和氮阱。 该方法提供了SONOS型设备中改进的存储器窗口。 在一个实施方案中，该方法包括氧化，氮化，再氧化和重新染色。 在一个实施方案中，首先用O 2进行氧化，并用NO进行再氧化。

公开(公告)号：US20080290399A1

公开(公告)日：2008-11-27

申请号：US11904475

申请日：2007-09-26

Applicant: Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

Inventor： Sagy Levy ,  Fredrick B. Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L21/336

CPC classification number: H01L29/792 ,  H01L21/28282 ,  H01L29/513 ,  H01L29/66833

Abstract: A nonvolatile charge trap memory device is described. The device includes a substrate having a channel region and a pair of source/drain regions. A gate stack is above the substrate over the channel region and between the pair of source/drain regions. The gate stack includes a multi-layer charge-trapping region having a first deuterated layer. The multi-layer charge-trapping region may further include a deuterium-free charge-trapping layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件。 该器件包括具有沟道区和一对源极/漏极区的衬底。 栅极堆叠在沟道区域上方之间以及在一对源极/漏极区域之间的衬底之上。 栅极堆叠包括具有第一氘化层的多层电荷捕获区域。 多层电荷俘获区域还可以包括不含氘的电荷俘获层。

公开(公告)号：US09716153B2

公开(公告)日：2017-07-25

申请号：US13539459

申请日：2012-07-01

Applicant: Sagy Levy ,  Fredrick Jenne ,  Krishnaswamy Ramkumar

Inventor： Sagy Levy ,  Fredrick Jenne ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  H01L29/40 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L29/78 ,  H01L29/786 ,  H01L29/04 ,  H01L29/06 ,  H01L29/16

CPC classification number: H01L29/408 ,  H01L21/28282 ,  H01L29/04 ,  H01L29/0676 ,  H01L29/16 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66833 ,  H01L29/785 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

Abstract: Scaling a charge trap memory device and the article made thereby. In one embodiment, the charge trap memory device includes a substrate having a source region, a drain region, and a channel region electrically connecting the source and drain. A tunnel dielectric layer is disposed above the substrate over the channel region, and a multi-layer charge-trapping region disposed on the tunnel dielectric layer. The multi-layer charge-trapping region includes a first deuterated layer disposed on the tunnel dielectric layer, a first nitride layer disposed on the first deuterated layer and a second nitride layer.

公开(公告)号：US09431549B2

公开(公告)日：2016-08-30

申请号：US13436875

申请日：2012-03-31

Applicant: Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

Inventor： Igor Polishchuk ,  Sagy Levy ,  Krishnaswamy Ramkumar

IPC: H01L29/792 ,  B82Y10/00 ,  H01L21/28 ,  H01L29/51 ,  H01L29/66 ,  H01L27/115

CPC classification number: H01L29/7923 ,  B82Y10/00 ,  H01L21/28282 ,  H01L27/11578 ,  H01L29/0676 ,  H01L29/42392 ,  H01L29/4908 ,  H01L29/513 ,  H01L29/517 ,  H01L29/518 ,  H01L29/66666 ,  H01L29/66742 ,  H01L29/66833 ,  H01L29/78642 ,  H01L29/78696 ,  H01L29/792 ,  H01L29/7926

Abstract: An embodiment of a nonvolatile charge trap memory device is described. In one embodiment, the device comprises a channel comprising silicon overlying a surface on a substrate electrically connecting a first diffusion region and a second diffusion region of the memory device, and a gate stack intersecting and overlying at least a portion of the channel, the gate stack comprising a tunnel oxide abutting the channel, a split charge-trapping region abutting the tunnel oxide, and a multi-layer blocking dielectric abutting the split charge-trapping region. The split charge-trapping region includes a first charge-trapping layer comprising a nitride closer to the tunnel oxide, and a second charge-trapping layer comprising a nitride overlying the first charge-trapping layer. The multi-layer blocking dielectric comprises at least a high-K dielectric layer.

Abstract translation: 描述了非易失性电荷陷阱存储器件的实施例。 在一个实施例中，该装置包括一个通道，该沟道包括覆盖在电连接存储器件的第一扩散区和第二扩散区的衬底上的表面的硅以及与沟道的至少一部分相交并且覆盖的栅极堆，栅极 包括邻接通道的隧道氧化物的堆叠，邻接隧道氧化物的分裂电荷捕获区域和与分离的电荷捕获区域邻接的多层阻挡电介质。 分离电荷捕获区域包括第一电荷捕获层，其包含更接近隧道氧化物的氮化物，以及包含覆盖在第一电荷俘获层上的氮化物的第二电荷俘获层。 多层阻挡电介质至少包括高K电介质层。