公开(公告)号：US5981353A

公开(公告)日：1999-11-09

申请号：US798154

申请日：1997-02-10

Applicant: Meng-Jin Tsai

Inventor： Meng-Jin Tsai

IPC: H01L21/762 ,  H01L21/76

CPC classification number: H01L21/76224

Abstract: A method of making a shallow trench isolation region which has a reduced kink effect at a subthreshold voltage by forming a shallow trench isolation region, including providing a silicon substrate having a front surface and a backside surface. A first pad oxide layer is c formed over the front surface, and a second pad oxide layer is currently formed over the backside surface. A first silicon nitride layer is formed over the first pad oxide layer, and a second silicon nitride layer is concurrently formed over the second pad oxide layer. The first silicon nitride layer, first pad oxide layer, and the silicon substrate are patterned to form a trench. A side-wall oxide layer is formed within the trench, and a first oxide layer is concurrently formed on a surface of the second silicon nitride layer. A second oxide layer is formed over the first silicon nitride layer and fills the trench. The first oxide layer is removed, and a portion of the second oxide layer is removed. The first silicon nitride layer and the second silicon nitride layer are removed. The removal of the first oxide layer and the subsequent steps are performed in sequence.

Abstract translation: 一种形成浅沟槽隔离区域的方法，该区域通过形成浅沟槽隔离区域而在亚阈值电压下具有降低的扭结效应，包括提供具有前表面和背面的硅衬底。 在前表面上形成第一衬垫氧化物层，并且第二衬垫氧化物层当前形成在背面上。 在第一焊盘氧化物层上形成第一氮化硅层，并且在第二焊盘氧化物层上同时形成第二氮化硅层。 将第一氮化硅层，第一焊盘氧化物层和硅衬底图案化以形成沟槽。 在沟槽内形成侧壁氧化物层，并且在第二氮化硅层的表面上同时形成第一氧化物层。 第二氧化物层形成在第一氮化硅层上并填充沟槽。 去除第一氧化物层，并且去除一部分第二氧化物层。 去除第一氮化硅层和第二氮化硅层。 依次进行第一氧化物层的除去和后续步骤。

公开(公告)号：US5712185A

公开(公告)日：1998-01-27

申请号：US636623

申请日：1996-04-23

Applicant: Meng-Jin Tsai ,  Water Lur ,  Chin-Lai Chen

Inventor： Meng-Jin Tsai ,  Water Lur ,  Chin-Lai Chen

IPC: H01L21/32 ,  H01L21/762 ,  H01L21/76

CPC classification number: H01L21/32 ,  H01L21/76224

Abstract: A method for forming shallow trench isolation without a recessed edge problem is disclosed. The present invention comprises forming a pad oxide layer on a substrate. Next, a silicon nitride layer is formed on the pad oxide, and a sacrificial layer is formed on the silicon nitride layer. A photo-resist layer that defines an active region on the sacrificial layer is applied. Thereafter, the portions of the sacrificial layer, the silicon nitride layer, the pad oxide layer and the substrate are removed to form a trench. Portions of the silicon nitride layer are undercut, and a dielectric layer is formed to fill the trench. The dielectric layer is planarized until the silicon nitride layer is exposed. Finally, the silicon nitride layer and the pad oxide layer are removed.

Abstract translation: 公开了一种用于形成没有凹陷边缘问题的浅沟槽隔离的方法。 本发明包括在衬底上形成衬垫氧化物层。 接下来，在衬垫氧化物上形成氮化硅层，在氮化硅层上形成牺牲层。 施加在牺牲层上限定有源区的光致抗蚀剂层。 此后，去除牺牲层，氮化硅层，衬垫氧化物层和衬底的部分以形成沟槽。 底切部分的氮化硅层，形成电介质层以填充沟槽。 平坦化电介质层，直至暴露氮化硅层。 最后，去除氮化硅层和衬垫氧化物层。

公开(公告)号：US20060084259A1

公开(公告)日：2006-04-20

申请号：US11245175

申请日：2005-10-07

Applicant: Meng-Jin Tsai

Inventor： Meng-Jin Tsai

IPC: H01L21/60

CPC classification number: H01L23/3171 ,  H01L23/525 ,  H01L24/11 ,  H01L24/12 ,  H01L2224/0231 ,  H01L2224/0401 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01006 ,  H01L2924/01075 ,  H01L2924/14

Abstract: A manufacturing method of wafer passivation layer and manufacturing method of wafer bump. First, a wafer is provided with an active surface, which has a passivation layer and reveals a plurality of bonding pads on said passivation. Next, a redistribution layer is formed on the wafer and is electrically connected with the bonding pad. Further, a dielectric layer is formed on the wafer to cover the redistribution layer. Then, said dielectric layer is cured, followed by a patterning process, so that part of the redistribution layer can be revealed from the passivation. Next, plasma cleaning is performed on the active surface of the wafer, and the dielectric layer is cured again. Further, a bumping process is performed. This manufacturing method of wafer passivation and manufacturing method of wafer bump can effectively reduce potential damages of the passivation in further processing procedures and enhance yields.

Abstract translation: 晶圆钝化层的制造方法及晶圆凸块的制造方法。 首先，晶片设置有活性表面，其具有钝化层并且在所述钝化上显露多个键合焊盘。 接下来，在晶片上形成再分配层，并且与接合焊盘电连接。 此外，在晶片上形成介电层以覆盖再分布层。 然后，使所述电介质层固化，然后进行图案化处理，从而可以从钝化中显露部分再分布层。 接着，对晶片的活性表面进行等离子体清洗，再次固化电介质层。 此外，进行碰撞处理。 晶片钝化的制造方法和晶片凸块的制造方法可以在进一步的处理过程中有效地减少钝化的潜在损害并提高产量。

公开(公告)号：US06190983B1

公开(公告)日：2001-02-20

申请号：US09430278

申请日：1999-10-29

Applicant: Meng-Jin Tsai

Inventor： Meng-Jin Tsai

IPC: H01L21336

CPC classification number: H01L29/66598 ,  H01L21/266 ,  H01L29/6659

Abstract: A method for providing triangle shapes of high-density plasma CVD film, thereby the grad and source/drain implantation can be applied in the same step, and an offset source/drain mask layer can be eliminated. A substrate is provided incorporating a device, wherein the device is defined as a high-voltage MOS region. Sequentially, a plurality of field oxides are formed on the substrate, one of the field oxides is spaced from another of the field oxides by a high-voltage MOS region. Then, a gate oxide layer is formed above the silicon substrate. Moreover, a polysilicon layer is deposited over the gate oxide layer. A photoresist layer is formed above the polysilicon layer and gate oxide layer, wherein the photoresist layer is defined and etched to form a gate. Then, the photoresist layer is removed. Consequentially, a dielectric layer is deposited and etched above the polysilicon layer by using high-density plasma CVD to result in the inherit triangle shape of high-density plasma CVD film characteristic. N-type ions are implanted into the silicon substrate to form N-type grad therein, and then N+-type ions only penetrate through the flat high-density plasma CVD dielectric film and not the triangle shape high-density plasma CVD film to form source/drain regions inside the N-type grad.

Abstract translation: 一种用于提供高密度等离子体CVD膜的三角形形状的方法，从而可以在相同的步骤中施加渐变和源极/漏极注入，并且可以消除偏移源极/漏极掩模层。 提供了一种结合有器件的衬底，其中该器件被定义为高电压MOS区。 接下来，在基板上形成多个场氧化物，其中一个场氧化物通过高压MOS区与另一个场氧化物隔开。 然后，在硅衬底上形成栅极氧化层。 此外，在栅极氧化物层上沉积多晶硅层。 在多晶硅层和栅极氧化物层上方形成光致抗蚀剂层，其中光致抗蚀剂层被限定和蚀刻以形成栅极。 然后，除去光致抗蚀剂层。 因此，通过使用高密度等离子体CVD沉积和蚀刻多晶硅层之上的电介质层以产生高密度等离子体CVD膜特性的继承三角形形状。 将N型离子注入到硅衬底中以形成N型渐变，然后N +型离子仅穿透扁平高密度等离子体CVD电介质膜而不是三角形形状的高密度等离子体CVD膜形成源 /漏区内N型梯度。

公开(公告)号：US6156640A

公开(公告)日：2000-12-05

申请号：US115184

申请日：1998-07-14

Applicant: Meng-Jin Tsai ,  Yimin Huang

Inventor： Meng-Jin Tsai ,  Yimin Huang

IPC: H01L21/027 ,  H01L21/768

CPC classification number: H01L21/76807 ,  H01L21/0276 ,  H01L21/76802 ,  H01L21/7684

Abstract: A method for improving the damascene process window for metallization utilizes an anti-reflective coating to increase the precision of the photolithography process. An inter-layer dielectric and an anti-reflective layer are formed in turn on a semiconductor substrate. The inter-layer dielectric is patterned to form the interconnecting line regions. A conductive layer is then deposited on the semiconductor substrate and fills the interconnecting line regions. The chemical mechanical polish is performed to remove a portion of the conductive layer exceeding the interconnect line regions and simultaneously remove residual portion of said anti-reflective layer.

Abstract translation: 用于改进用于金属化的镶嵌工艺窗口的方法利用抗反射涂层来提高光刻工艺的精度。 依次在半导体衬底上形成层间电介质和抗反射层。 将层间电介质图案化以形成互连线区域。 然后将导电层沉积在半导体衬底上并填充互连线区域。 执行化学机械抛光以去除超过互连线区域的导电层的一部分，并同时去除所述抗反射层的残留部分。

公开(公告)号：US5926729A

公开(公告)日：1999-07-20

申请号：US877204

申请日：1997-06-17

Applicant: Meng-Jin Tsai ,  Heng-Sheng Huang

Inventor： Meng-Jin Tsai ,  Heng-Sheng Huang

IPC: H01L21/8234 ,  H01L21/70

CPC classification number: H01L21/823462 ,  Y10S438/981

Abstract: A method is provided for use in semiconductor fabrication processes for forming a plurality of gate oxide layers with various predefined thicknesses in mixed-mode or embedded circuits that are formed in a semiconductor substrate. In particular, the gate oxide layers of various predefined thicknesses are formed by means of separated growth, which allows all the gate oxide layers to be each formed in one single step, instead of combining two or more oxide layers as in conventional processes, so that the thicknesses can be more easily controllable to the desired levels. The quality of the thus-formed gate oxide layers can thus be better assured.

Abstract translation: 提供了一种在半导体制造工艺中使用的方法，用于在形成在半导体衬底中的混合模式或嵌入电路中形成具有各种预定厚度的多个栅极氧化物层。 特别地，通过分离的生长形成各种预定厚度的栅极氧化物层，这允许在一个单一步骤中形成所有栅极氧化物层，而不是如在常规工艺中组合两个或更多个氧化物层，使得 厚度可以更容易地控制到期望的水平。 因此可以更好地保证这样形成的栅极氧化物层的质量。

公开(公告)号：US5920779A

公开(公告)日：1999-07-06

申请号：US903595

申请日：1997-07-31

Applicant: Shih-Wei Sun ,  Meng-Jin Tsai

Inventor： Shih-Wei Sun ,  Meng-Jin Tsai

IPC: H01L21/8239 ,  H01L21/8242 ,  H01L21/8232

CPC classification number: H01L27/1052 ,  H01L27/10852 ,  H01L27/10873 ,  H01L27/10894 ,  Y10S148/116 ,  Y10S438/981

Abstract: Different thicknesses of gate oxide can be formed on a single chip in a single oxidation process by selectively implanting nitrogen into the surface of the chip in a pattern corresponding to the desired differences in gate oxide thickness. Implanting nitrogen to a silicon substrate reduces the rate at which oxide grows on the surface. Thus, by implanting different dosages of nitrogen into the surface of the substrate, thicker or thinner oxide layers can be provided. A processing chip with embedded DRAM can then be formed where the logic circuitry has a thin gate oxide and the DRAM circuitry has a thick gate oxide by implanting the higher dosage of nitrogen into the region of the chip where the logic circuits are to be formed. Different gate oxide thicknesses are then provided by exposing both the logic circuitry and the embedded DRAM section to a single thermal oxidation process.

Abstract translation: 可以在单个氧化工艺中的单个芯片上形成不同厚度的栅极氧化物，通过以对应于栅极氧化物厚度的期望差异的图案选择性地将氮气注入到芯片的表面中。 将氮气注入硅衬底会降低氧化物在表面上生长的速率。 因此，通过将不同剂量的氮注入到衬底的表面中，可以提供更厚或更薄的氧化物层。 然后可以形成具有嵌入式DRAM的处理芯片，其中逻辑电路具有薄栅极氧化物，并且DRAM电路通过将较高剂量的氮注入到要形成逻辑电路的芯片的区域中而具有厚栅极氧化物。 然后通过将逻辑电路和嵌入式DRAM部分暴露于单个热氧化工艺来提供不同的栅极氧化物厚度。

公开(公告)号：US5500545A

公开(公告)日：1996-03-19

申请号：US394585

申请日：1995-02-27

Applicant: Kuang-Chung Cheng ,  Meng-Jin Tsai ,  Ta-Chi Kuo ,  Kuo-Jaan Su

Inventor： Kuang-Chung Cheng ,  Meng-Jin Tsai ,  Ta-Chi Kuo ,  Kuo-Jaan Su

IPC: H01L29/786 ,  H01L21/36 ,  H01L21/26

CPC classification number: H01L29/78648 ,  H01L29/78696 ,  Y10S438/958

Abstract: A field effect transistor has been developed with one source and one drain but with two independent active regions. It is shown how a double switching characteristic can be obtained with this structure which is described along with a process for its manufacture.

Abstract translation: 场效应晶体管已开发出一个源极和一个漏极，但具有两个独立的有源区。 示出了如何利用与其制造方法一起描述的这种结构来获得双重切换特性。

公开(公告)号：US06403487B1

公开(公告)日：2002-06-11

申请号：US08991192

申请日：1997-12-16

Applicant: Cheng-Han Huang ,  Meng-Jin Tsai ,  Cheng-Jung Hsu ,  Po-Hung Chen

Inventor： Cheng-Han Huang ,  Meng-Jin Tsai ,  Cheng-Jung Hsu ,  Po-Hung Chen

IPC: H01L21302

CPC classification number: H01L21/823468 ,  H01L21/823456 ,  H01L27/105 ,  H01L29/6653

Abstract: A method is provided for forming separated spacer structures in a mixed-mode integrated circuit, which can be used to form spacer structures with different widths for the various kinds of devices in the mixed-mode integrated circuit. The method is for use on a semiconductor substrate which is formed with at least a first gate for a first kind of device of the mixed-mode integrated circuit and a second gate for a second kind of device of the integrated circuit, with the second gate being larger in width than the first gate such that the first gate is formed with a first spacer structure on the sidewalls thereof to a first desired width while the second gate is formed with a second spacer structure on the sidewalls thereof to a second desired width larger than the first desired width. The method features a two-step etching process in which the first etching process is performed to form one spacer structure to the first desired width, while the second etching process is performed to form the other spacer structure to the second desired width.

Abstract translation: 提供了一种用于在混合模式集成电路中形成分离的间隔结构的方法，其可用于形成用于混合模式集成电路中的各种装置的具有不同宽度的间隔结构。 该方法用于半导体衬底，该半导体衬底至少形成用于混合模式集成电路的第一种器件的第一栅极和集成电路的第二种器件的第二栅极，第二栅极 宽度大于第一栅极，使得第一栅极在其侧壁上形成具有第一间隔结构的第一期望宽度，而第二栅极在其侧壁上形成第二间隔结构，使其具有更大的第二期望宽度 比第一个期望的宽度。 该方法具有两步蚀刻工艺，其中执行第一蚀刻工艺以将第一蚀刻工艺形成为第一所需宽度，同时执行第二蚀刻工艺以形成另一间隔物结构至第二所需宽度。

公开(公告)号：US06232197B1

公开(公告)日：2001-05-15

申请号：US09287880

申请日：1999-04-07

Applicant: Meng-Jin Tsai

Inventor： Meng-Jin Tsai

IPC: H01L2120

CPC classification number: H01L28/40

Abstract: A metal-insulator-metal capacitor for improved mixed-mode capacitor in a logic circuit of a semiconductor device is disclosed. The bottom electrode of the capacitor is polycide and the top electrode is metal formed by damascene technology. The middle layer of the capacitor is a dielectric layer formed by using a chemical vapor deposition method. The voltage coefficient of this capacitor is approximate to zero.

Abstract translation: 公开了一种在半导体器件的逻辑电路中用于改进混合电容器的金属 - 绝缘体 - 金属电容器。 电容器的底部电极是聚硅氧烷，顶部电极是通过镶嵌技术形成的金属。 电容器的中间层是通过使用化学气相沉积法形成的电介质层。 该电容器的电压系数近似为零。