公开(公告)号：US20100103726A1

公开(公告)日：2010-04-29

申请号：US12652842

申请日：2010-01-06

Applicant: Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

Inventor： Jun-Soo BAE ,  Kwang-Jin LEE ,  Beak-Hyung CHO ,  Woo-Yeong CHO ,  Hye-Jin KIM

IPC: G11C11/00 ,  G11C7/02 ,  G11C5/14

CPC classification number: G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

Abstract translation: 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US20090251954A1

公开(公告)日：2009-10-08

申请号：US12417679

申请日：2009-04-03

Applicant: Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

Inventor： Qi WANG ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Taek-Sung KIM ,  Kwang-Ho KIM ,  Hyun-Ho CHOI

IPC: G11C11/00 ,  G11C8/00 ,  G11C11/416

CPC classification number: G11C16/08 ,  G11C8/12

Abstract: Disclosed is a semiconductor memory device including a memory cell array having a plurality of variable resistance memory cells divided into first and second areas. An I/O circuit is configured to access the memory cell array under the control of control logic so as to access the first or second area in response to an external command. The I/O circuit accesses the first area using a memory cell unit and the second area using a page unit.

Abstract translation: 公开了一种半导体存储器件，包括具有分成第一和第二区域的多个可变电阻存储器单元的存储单元阵列。 I / O电路被配置为在控制逻辑的控制下访问存储单元阵列，以响应于外部命令访问第一或第二区域。 I / O电路使用存储单元单元访问第一区域，并且使用页面单元访问第二区域。

公开(公告)号：US20090003049A1

公开(公告)日：2009-01-01

申请号：US12168742

申请日：2008-07-07

Applicant: Kwang-Jin LEE ,  Du-Eung KIM ,  Sang-Beom KANG ,  Woo-Yeong CHO

Inventor： Kwang-Jin LEE ,  Du-Eung KIM ,  Sang-Beom KANG ,  Woo-Yeong CHO

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C5/145 ,  G11C7/1078 ,  G11C7/1096 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

Abstract: A phase change memory device includes a memory cell having a phase change material, a write driver adapted to supply a program current to the memory cell during a programming interval, and a pump circuit adapted to enhance a current supply capacity of the write driver during the programming interval. The pump circuit is activated prior to the programming interval in response to an external control signal.

Abstract translation: 相变存储器件包括具有相变材料的存储单元，适于在编程间隔期间向存储单元提供编程电流的写入驱动器，以及用于在写入驱动器期间增强写入驱动器的电流供应容量的泵电路 编程间隔。 泵电路响应于外部控制信号在编程间隔之前被激活。

公开(公告)号：US20080291715A1

公开(公告)日：2008-11-27

申请号：US12116295

申请日：2008-05-07

Applicant: Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

Inventor： Mu-Hui PARK ,  Kwang-Jin LEE ,  Du-Eung KIM ,  Hye-Jin KIM ,  Woo-Yeong CHO

IPC: G11C11/00 ,  G11C7/00

CPC classification number: G11C13/0038 ,  G11C7/04 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/004 ,  G11C29/02 ,  G11C29/026 ,  G11C29/028

Abstract: A nonvolatile memory device includes a nonvolatile memory cell, a read circuit and a control bias generating circuit. The nonvolatile memory cell has a resistance level that changes depending on stored data. The read circuit reads the resistance level of the nonvolatile memory cell by receiving a control bias and supplying the nonvolatile memory cell a read bias based on the control bias. The control bias generating circuit receives an input bias, generates the control bias based on the input bias and supplies the control bias to the read circuit. A slope of the control bias to the input bias is less than 1.

Abstract translation: 非易失性存储器件包括非易失性存储单元，读取电路和控制偏置产生电路。 非易失性存储单元具有根据存储的数据而改变的电阻水平。 读取电路通过接收控制偏置来读取非易失性存储单元的电阻电平，并且基于控制偏压向非易失性存储单元提供读取偏置。 控制偏置产生电路接收输入偏置，基于输入偏置产生控制偏压，并将控制偏压提供给读取电路。 对输入偏置的控制偏置的斜率小于1。

公开(公告)号：US20080159017A1

公开(公告)日：2008-07-03

申请号：US11955562

申请日：2007-12-13

Applicant: Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

Inventor： Hye-Jin KIM ,  Kwang-Jin LEE ,  Woo-Yeong CHO ,  Mu-Hui PARK

IPC: G11C5/14

CPC classification number: G11C13/004 ,  G11C5/147 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C16/30 ,  G11C2013/0054 ,  G11C2213/72

Abstract: There are provided a bias voltage generator, a semiconductor memory device having the bias voltage generator, and a method for generating the bias voltage. The bias voltage generator which generates the bias voltage to control a sensing current supplied to a memory cell for sensing data is characterized in that the bias voltage is output in response to an input voltage being applied, so that a slope of the bias voltage to the input voltage is different in at least two sections divided corresponding to a level of the input voltage.

Abstract translation: 提供了偏置电压发生器，具有偏置电压发生器的半导体存储器件以及用于产生偏置电压的方法。 产生用于控制提供给存储单元的感测电流以感测数据的偏置电压的偏置电压发生器的特征在于，响应于所施加的输入电压而输出偏置电压，使得偏置电压的斜率 至少两个部分的输入电压不同，对应于输入电压的电平。