公开(公告)号：US08259511B2

公开(公告)日：2012-09-04

申请号：US13064672

申请日：2011-04-07

申请人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

发明人： Beak-Hyung Cho ,  Woo-Yeong Cho ,  Mu-Hui Park

IPC分类号： G11C7/10

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72

摘要： A phase change memory device may include a memory cell array, a write driver, and/or a control unit. The memory cell array may include a plurality of memory cells. The write driver may be configured to provide a program current to the memory cell array for setting a state of a phase change material to program a selected memory cell. The write driver may be configured to provide the program current such that the program current has a plurality of steps. The control unit may be configured to receive step information for adjusting a magnitude and a width of each step of the program current during a test operation and provide the step information to the write driver during a normal operation.

摘要翻译： 相变存储器件可以包括存储单元阵列，写入驱动器和/或控制单元。 存储单元阵列可以包括多个存储单元。 写入驱动器可以被配置为向存储器单元阵列提供程序电流，用于设置相变材料的状态以对选定的存储单元进行编程。 写驱动器可以被配置为提供程序电流，使得程序电流具有多个步骤。 控制单元可以被配置为在测试操作期间接收用于调整程序电流的每个步骤的幅度和宽度的步骤信息，并且在正常操作期间将该步骤信息提供给写入驱动器。

公开(公告)号：US08179711B2

公开(公告)日：2012-05-15

申请号：US12273225

申请日：2008-11-18

申请人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

发明人： Sung-min Kim ,  Eun-jung Yun ,  Jong-soo Seo ,  Du-eung Kim ,  Beak-hyung Cho ,  Byung-seo Kim

IPC分类号： G11C11/00

CPC分类号： G11C13/003 ,  G11C5/02 ,  G11C7/18 ,  G11C11/15 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0071 ,  G11C2213/71 ,  G11C2213/74 ,  G11C2213/79 ,  H01L27/24

摘要： In a semiconductor memory device and method, resistive-change memory cells are provided, each including a plurality of control transistors formed on different layers and variable resistance devices comprising a resistive-change memory. Each resistive-change memory cell includes a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In one example, the number of the control transistors is two. The semiconductor memory device includes a global bit line; a plurality of local bit lines connected to or disconnected from the global bit line via local bit line selection circuits which correspond to the local bit lines, respectively; and a plurality of resistive-change memory cell groups storing data while being connected to the local bit lines, respectively. Each of the resistive-change memory cells of each of the resistive-change memory cell groups comprises a plurality of control transistors formed on different layers, and a variable resistance device formed of a resistive-change memory. In addition, the semiconductor memory device has a hierarchical bit line structure that uses a global bit line and local bit lines. Accordingly, it is possible to increase both the integration density of the semiconductor memory device and the amount of current flowing through each of the resistive-change memory cells.

摘要翻译： 在半导体存储器件和方法中，提供了电阻变化存储单元，每个包括形成在不同层上的多个控制晶体管和包括电阻变化存储器的可变电阻器件。 每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 在一个示例中，控制晶体管的数量是两个。 半导体存储器件包括全局位线; 通过分别对应于本地位线的本地位线选择电路分别连接到全局位线或与全局位线断开的多个局部位线; 以及分别在连接到本地位线时存储数据的多个电阻变化存储单元组。 每个电阻变化存储单元组中的每个电阻变化存储单元包括形成在不同层上的多个控制晶体管和由电阻变化存储器形成的可变电阻器件。 此外，半导体存储器件具有使用全局位线和局部位线的分层位线结构。 因此，可以增加半导体存储器件的集成密度和流过每个电阻变化存储单元的电流量。

公开(公告)号：US08040719B2

公开(公告)日：2011-10-18

申请号：US12323583

申请日：2008-11-26

申请人： Beak-hyung Cho ,  Yong-seok Jeon ,  Hye-jin Kim

发明人： Beak-hyung Cho ,  Yong-seok Jeon ,  Hye-jin Kim

IPC分类号： G11C11/00

CPC分类号： G11C7/12 ,  G11C7/18 ,  G11C13/0004 ,  G11C13/0026 ,  G11C13/004 ,  G11C2213/72

摘要： A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines.

摘要翻译： 存储器件包括其中具有多个行和列的非易失性存储器单元（例如，PRAM单元）的存储器阵列和电耦合到存储器阵列中的对应的第一多列存储器单元的第一多个局部位线。 还提供了响应于位线选择信号的第一多个位线选择电路。 第一多个位线放电电路电连接到第一多个局部位线中的相应的位线。 提供位线放电控制电路以在操作期间用等效的位线放电信号驱动第一多个位线放电电路，以从第一多个局部位线中的所选择的一个读取数据。

公开(公告)号：US20110242886A1

公开(公告)日：2011-10-06

申请号：US13091238

申请日：2011-04-21

申请人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

发明人： Beak-Hyung Cho ,  Du-Eung Kim ,  Woo-Yeong Cho

IPC分类号： G11C11/21

CPC分类号： G11C13/0069 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092

摘要： Apparatus and systems that use phase-change memory devices are provided. The phase-change memory devices may include multiple phase-change memory cells and a reset pulse generation circuit configured to output multiple sequential reset pulses. Each sequential reset pulse is output to a corresponding one of multiple reset lines. Multiple write driver circuits are coupled to corresponding phase change memory cells and to a corresponding one of the reset lines of the reset pulse generation circuit.

摘要翻译： 提供了使用相变存储器件的装置和系统。 相变存储器件可以包括多个相变存储器单元和被配置为输出多个顺序复位脉冲的复位脉冲发生电路。 每个顺序复位脉冲被输出到多个复位线中相应的一个。 多个写入驱动器电路耦合到相应的相变存储器单元和复位脉冲发生电路的相应的一个复位线。

公开(公告)号：US08023319B2

公开(公告)日：2011-09-20

申请号：US12457319

申请日：2009-06-08

申请人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

发明人： Beak-Hyung Cho ,  Byung-Gil Choi ,  Joon-Min Park

IPC分类号： G11C11/00

CPC分类号： G11C29/808 ,  G11C13/0004

摘要： The phase change memory device includes a plurality of memory banks, a plurality of local conductor lines connected to the plurality of memory banks, at least one global conductor line connected to the plurality of local conductor lines, and at least one repair control circuit configured to selectively replace at least one of the at least one global conductor line with at least one redundant global conductor line and configured to selectively replace at least one of the plurality of local conductor lines with at least one redundant local conductor line.

摘要翻译： 所述相变存储器件包括多个存储体，连接到所述多个存储体的多个局部导体线，连接到所述多个局部导体线的至少一个全局导体线，以及至少一个修理控制电路， 选择性地将所述至少一个全局导体线中的至少一个与至少一个冗余全局导体线替换并且被配置为用至少一个冗余局部导体线选择性地替换所述多条局部导体线中的至少一个。

公开(公告)号：US07936594B2

公开(公告)日：2011-05-03

申请号：US12437438

申请日：2009-05-07

申请人： Joon Min Park ,  Beak Hyung Cho

发明人： Joon Min Park ,  Beak Hyung Cho

IPC分类号： G11C11/00

CPC分类号： G11C8/10 ,  G11C7/18 ,  G11C8/14 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0088 ,  G11C2213/77

摘要： A semiconductor memory device having an efficient core structure for multi-writing includes a data input/output line, a plurality of memory banks each comprising a plurality of memory cells, a first global bit line and a second global bit line which are shared by the plurality of memory banks, and a first write driver and a second write driver which are connected with the data input/output line and provide a program current to the plurality of memory banks through the first and second global bit lines, respectively. Each memory bank includes a first cell area connected with the first global bit line and a second cell area connected with the second global bit line. In a multi-write mode, the first cell area in a first memory bank among the plurality of memory banks and the second cell area in a second memory bank among the plurality of memory banks are simultaneously selected and data is written to memory cells in the selected first and second cell areas, so that data writing time is reduced under the same conditions as a normal write mode.

摘要翻译： 具有用于多次写入的有效核心结构的半导体存储器件包括数据输入/输出线，多个存储器组，每个存储器组包括多个存储器单元，第一全局位线和第二全局位线， 多个存储体，以及分别与数据输入/输出线连接并通过第一和第二全局位线向多个存储体提供编程电流的第一写入驱动器和第二写入驱动器。 每个存储体包括与第一全局位线连接的第一单元区域和与第二全局位线连接的第二单元区域。 在多写入模式中，同时选择多个存储体中的第一存储体中的第一单元区域和多个存储体之间的第二存储体中的第二单元区域，并将数据写入存储单元中的存储单元 选择的第一和第二单元区域，使得在与正常写入模式相同的条件下数据写入时间被减少。

公开(公告)号：US07864619B2

公开(公告)日：2011-01-04

申请号：US12292200

申请日：2008-11-13

申请人： Beak-hyung Cho ,  Kwang-ho Kim ,  Young-pil Kim

发明人： Beak-hyung Cho ,  Kwang-ho Kim ,  Young-pil Kim

IPC分类号： G11C8/00 ,  G11C5/14 ,  G11C11/00

CPC分类号： G11C13/0038 ,  G11C8/08 ,  G11C13/0004 ,  G11C13/0028 ,  G11C13/0069 ,  G11C2013/0078

摘要： A write driver circuit for a memory that includes phase-change memory cells changeable between a RESET state resistance and a SET state resistance in response to an applied current pulse, the write driver circuit including a write current level adjusting unit configured to determine first to n-th SET state current levels in response to a SET state current level signal, where n is an integer greater than 1, and configured to determine a RESET state current level in response to a RESET state current level signal, and a write current output unit configured to generate one of a SET state current pulse and a RESET state current pulse corresponding to a SET state current level or a RESET state current level determined by the write current level adjusting unit.

摘要翻译： 一种用于存储器的写入驱动器电路，其包括响应于所施加的电流脉冲而在RESET状态电阻和SET状态电阻之间改变的相变存储器单元，所述写入驱动器电路包括写入电平电平调整单元，其被配置为从第一至第n 响应于SET状态电流电平信号，其中n是大于1的整数，并且被配置为响应于RESET状态电流信号确定RESET状态电流电平，并且写入电流输出单元 被配置为产生与由写入电平电平调整单元确定的SET状态电流电平或RESET状态电流电平对应的SET状态电流脉冲和RESET状态电流脉冲之一。

公开(公告)号：US07751232B2

公开(公告)日：2010-07-06

申请号：US11953146

申请日：2007-12-10

申请人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

发明人： Chang-Soo Lee ,  Hyung-Rok Oh ,  Beak-Hyung Cho ,  Kwang-Jin Lee

IPC分类号： G11C11/00

CPC分类号： G11C29/08 ,  G11C13/0004

摘要： A method of testing PRAM devices is disclosed. The method simultaneously writes input data to a plurality of memory banks by writing set data to a first group of memory banks and writing reset data to a second group of memory banks, performs a write operation test by comparing data read from the plurality of memory banks with corresponding input data, and determines a fail cell in relation to the test results.

摘要翻译： 公开了一种测试PRAM设备的方法。 该方法通过将设置数据写入第一组存储体并将复位数据写入第二组存储体，同时将输入数据写入多个存储体，通过比较从多个存储体读取的数据执行写操作测试 与相应的输入数据相关，并确定与测试结果相关的故障单元。

公开(公告)号：US07688621B2

公开(公告)日：2010-03-30

申请号：US11949299

申请日：2007-12-03

申请人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

发明人： Beak-hyung Cho ,  Woo-yeong Cho ,  Hyung-rok Oh

IPC分类号： G11C11/00

CPC分类号： G11C7/1078 ,  G11C7/1096 ,  G11C13/0004 ,  G11C13/0069 ,  G11C2013/0078 ,  G11C2213/79

摘要： An apparatus, a nonvolatile memory device and a nonvolatile memory system include an array of nonvolatile variable resistive memory (VRM) cells and a writing driver circuit having a pulse selection circuit, a current control circuit, and a current drive circuit. The current control circuit receives a bias voltage, outputs a control signal at a second level during an enable duration of the reset pulse when the data is at a first level, and outputs a control signal at a first level during an enable duration of the set pulse when the data is at a second level. The current drive circuit outputs writing current to the phase-change memory array during the enable duration of the reset pulse or the set pulse. The writing driver circuit can select the reset pulse or the set pulse according to the logic level of the data, and control the level of current applied to the phase-change memory array according to the reset pulse or the set pulse.

摘要翻译： 一种装置，非易失性存储装置和非易失性存储器系统包括易失性可变电阻存储器（VRM）单元阵列和具有脉冲选择电路，电流控制电路和电流驱动电路的写入驱动器电路。 电流控制电路接收偏置电压，当数据处于第一电平时，在复位脉冲的使能持续时间期间以第二电平输出控制信号，并且在该组的使能持续时间期间输出处于第一电平的控制信号 数据处于第二级时的脉冲。 当前驱动电路在复位脉冲或设定脉冲的使能期间内向相变存储器阵列输出写入电流。 写入驱动器电路可以根据数据的逻辑电平选择复位脉冲或设置脉冲，并根据复位脉冲或设定脉冲控制施加到相变存储器阵列的电流电平。

公开(公告)号：US07580278B2

公开(公告)日：2009-08-25

申请号：US11868992

申请日：2007-10-09

申请人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

发明人： Beak-Hyung Cho ,  Jong-Soo Seo ,  Won-Seok Lee

IPC分类号： G11C11/00

CPC分类号： G11C13/0069 ,  G11C11/5678 ,  G11C13/0004 ,  G11C2013/0078 ,  G11C2013/0092 ,  G11C2213/72 ,  G11C2213/79

摘要： A variable resistance memory device includes a memory cell array having a plurality of memory cells, a write driver which supplies a step-down set current to the memory cells, where the step-down set current includes a plurality of successive steps of decreasing current magnitude, and a set program control circuit which controls a duration of the step-down set current supplied by the write driver. The set program control circuit controls the duration of the step-down set current in accordance with at least one of data contained in an mode register set (MRS) and a conductive state of a fuse element.

摘要翻译： 可变电阻存储器件包括具有多个存储器单元的存储单元阵列，一个写入驱动器，其将降压设定电流提供给存储器单元，其中降压设定电流包括多个连续的步骤，其降低电流幅度 以及控制由写入驱动器提供的降压设定电流的持续时间的设定程序控制电路。 设定程序控制电路根据包含在模式寄存器组（MRS）和熔丝元件的导通状态中的至少一个数据来控制降压设定电流的持续时间。