公开(公告)号：US20160155934A1

公开(公告)日：2016-06-02

申请号：US14887506

申请日：2015-10-20

Applicant: Kyu-Man HWANG ,  Shi-Jung KIM ,  Mi-Lim PARK ,  Jun-Soo BAE ,  Seung-Woo LEE

Inventor： Kyu-Man HWANG ,  Shi-Jung KIM ,  Mi-Lim PARK ,  Jun-Soo BAE ,  Seung-Woo LEE

IPC: H01L43/08 ,  H01L43/02 ,  H01L43/12

CPC classification number: H01L43/08 ,  H01L43/12

Abstract: Magnetic random access memory (MRAM) devices, and methods of manufacturing the same, include at least one first magnetic material pattern on a substrate, at least one second magnetic material pattern on the at least one first magnetic material pattern, and at least one tunnel barrier layer pattern between the at least one first magnetic material pattern and the at least one second magnetic material pattern. A width of a top surface of the at least one first magnetic material pattern may be less than a width of a bottom surface of the at least one second magnetic material pattern.

Abstract translation: 磁性随机存取存储器（MRAM）器件及其制造方法包括在衬底上的至少一个第一磁性材料图案，至少一个第一磁性材料图案上的至少一个第二磁性材料图案，以及至少一个隧道 所述至少一个第一磁性材料图案和所述至少一个第二磁性材料图案之间的阻挡层图案。 所述至少一个第一磁性材料图案的顶表面的宽度可以小于所述至少一个第二磁性材料图案的底表面的宽度。

公开(公告)号：US08143653B2

公开(公告)日：2012-03-27

申请号：US12619016

申请日：2009-11-16

Applicant: Woo-Yeong Cho ,  Jong-Soo Seo ,  Young-Kug Moon ,  Jun-Soo Bae ,  Kwang-Jin Lee

Inventor： Woo-Yeong Cho ,  Jong-Soo Seo ,  Young-Kug Moon ,  Jun-Soo Bae ,  Kwang-Jin Lee

IPC: H01L29/66

CPC classification number: G11C13/0064 ,  G11C7/04 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0023 ,  G11C13/0026 ,  G11C13/004 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078 ,  G11C2213/72 ,  H01L27/2409 ,  H01L29/868 ,  H01L45/06 ,  H01L45/1233 ,  H01L45/141 ,  H01L45/143 ,  H01L45/144 ,  H01L45/148

Abstract: A phase-change random access memory device is provided. The phase-change random access memory device includes a global bit line connected to a write circuit and a read circuit, multiple local bit lines, each being connected to multiple phase-change memory cells, and multiple column select transistors selectively connecting the global bit line with each of the multiple local bit lines, each column select transistor having a resistance that varies depending on its distance from the write circuit and the read circuit.

Abstract translation: 提供了相变随机存取存储器件。 相变随机存取存储器件包括连接到写入电路和读取电路的全局位线，每个连接到多个相变存储器单元的多个局部位线，以及选择性地连接全局位线的多个列选择晶体管 对于多个局部位线中的每一个，每个列选择晶体管具有根据其与写入电路和读取电路的距离而变化的电阻。

公开(公告)号：US08134866B2

公开(公告)日：2012-03-13

申请号：US12652842

申请日：2010-01-06

Applicant: Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

Inventor： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho ,  Woo-Yeong Cho ,  Hye-Jin Kim

IPC: G11C11/00

CPC classification number: G11C8/10 ,  G11C5/143 ,  G11C5/145 ,  G11C11/56 ,  G11C11/5678 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0061 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0076 ,  G11C2013/0078

Abstract: A method programs a phase change memory device. The method comprises receiving program data for selected memory cells; generating bias voltages based on reference cells; sensing read data stored in a selected memory cell by supplying the selected memory cell with verification currents determined by the bias voltages; determining whether the read data is identical to the program data; and upon determining that the program data for one or more of the selected memory cells is not identical to the corresponding read data, iteratively applying a write current to the one or more selected memory cells.

Abstract translation: 一种方法对相变存储器件进行编程。 该方法包括接收所选存储单元的程序数据; 基于参考单元产生偏置电压; 通过向所选择的存储器单元提供由偏置电压确定的验证电流来感测存储在所选存储单元中的读取数据; 确定读取的数据是否与节目数据相同; 并且一旦确定所选存储器单元中的一个或多个的程序数据与相应的读取数据不同，则迭代地向一个或多个所选择的存储器单元施加写入电流。

公开(公告)号：US20110080775A1

公开(公告)日：2011-04-07

申请号：US12893413

申请日：2010-09-29

Applicant: Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho

Inventor： Jun-Soo Bae ,  Kwang-Jin Lee ,  Beak-Hyung Cho

IPC: G11C11/00 ,  G11C7/04

CPC classification number: G11C8/12 ,  G11C7/04 ,  G11C11/5678 ,  G11C11/5685 ,  G11C13/0004 ,  G11C13/0007 ,  G11C13/004 ,  G11C2013/0054 ,  G11C2211/5634

Abstract: A nonvolatile memory device includes a memory cell array including a plurality of nonvolatile memory cells each having a resistance corresponding to one of a plurality of first resistance distributions, a temperature compensation circuit including one or more reference cells each having a resistance corresponding to one among one or more second resistance distributions, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit being adapted to supply compensation current to a sensing node, an amount of the compensation current varying based on the resistance of each reference cell, and the sense amplifier being adapted to compare the level of the sensing node with a reference level and to output a comparison result.

Abstract translation: 非易失性存储器件包括存储单元阵列，其包括多个非易失性存储单元，每个非易失性存储单元具有对应于多个第一电阻分布之一的电阻，温度补偿电路包括一个或多个参考单元，每个参考单元具有对应于一个 或更多的第二电阻分布，以及包括补偿单元和读出放大器的数据读取电路，所述补偿单元适于向感测节点提供补偿电流，所述补偿电流的量基于每个参考单元的电阻而变化， 并且所述读出放大器适于将感测节点的电平与参考电平进行比较并输出比较结果。

公开(公告)号：US20100085799A1

公开(公告)日：2010-04-08

申请号：US12632018

申请日：2009-12-07

Applicant: Woo-Yeong CHO ,  Ki-Sung KIM ,  Du-Eung KIM ,  Kwang-Jin LEE ,  Jun-Soo BAE

Inventor： Woo-Yeong CHO ,  Ki-Sung KIM ,  Du-Eung KIM ,  Kwang-Jin LEE ,  Jun-Soo BAE

IPC: G11C11/00 ,  G11C7/02 ,  G11C7/00

CPC classification number: G11C11/5678 ,  G11C7/04 ,  G11C13/0004 ,  G11C13/0038 ,  G11C13/004 ,  G11C13/0064 ,  G11C13/0069 ,  G11C2013/0054 ,  G11C2013/0078 ,  G11C2211/5634

Abstract: Disclosed is a method of driving a multi-level variable resistive memory device. A method of driving a multi-level variable resistive memory device includes supplying a write current to a variable resistive memory cell so as to change resistance of the variable resistive memory cell, verifying whether or not changed resistance enters a predetermined resistance window, the intended resistance window depending on the resistance of reference cells, and supplying a write current having an increased or decreased amount from the write current supplied most recently on the basis of the verification result so as to change resistance of the variable resistive memory cell.

Abstract translation: 公开了一种驱动多电平可变电阻存储器件的方法。 驱动多电平可变电阻存储器件的方法包括向可变电阻存储器单元提供写入电流，以便改变可变电阻存储器单元的电阻，验证改变的电阻是否进入预定的电阻窗，预期电阻 窗口，取决于参考单元的电阻，并且基于验证结果从最近提供的写入电流提供具有增加或减少的量的写入电流，以便改变可变电阻存储单元的电阻。

公开(公告)号：US07582568B2

公开(公告)日：2009-09-01

申请号：US11625142

申请日：2007-01-19

Applicant: Young-Soo Lim ,  Jun-Soo Bae

Inventor： Young-Soo Lim ,  Jun-Soo Bae

IPC: H01L21/302

CPC classification number: H01L45/1233 ,  H01L45/06 ,  H01L45/144 ,  H01L45/1675

Abstract: The present invention relates to a method of forming a phase changeable structure wherein an upper electrode is formed on a phase changeable layer. A material including fluorine can be provided to the phase changeable layer and the upper electrode. The phase changeable layer can be etched to form a phase changeable pattern. Oxygen plasma or water vapor plasma can then be provided to the upper electrode and the phase changeable pattern.

Abstract translation: 本发明涉及形成可变相结构的方法，其中上电极形成在相变层上。 可以向相变层和上电极提供包含氟的材料。 相变层可被蚀刻以形成相变图案。 然后可以将氧等离子体或水蒸气等离子体提供给上电极和相变图案。

公开(公告)号：US20090004773A1

公开(公告)日：2009-01-01

申请号：US12189477

申请日：2008-08-11

Applicant: Jeong-Hee Park ,  Ju-Chul Park ,  Jun-Soo Bae ,  Bong-Jin Kuh ,  Yong-Ho Ha

Inventor： Jeong-Hee Park ,  Ju-Chul Park ,  Jun-Soo Bae ,  Bong-Jin Kuh ,  Yong-Ho Ha

IPC: H01L45/00

CPC classification number: H01L45/06 ,  G11C13/0004 ,  G11C2213/79 ,  H01L45/1233 ,  H01L45/143 ,  H01L45/144 ,  H01L45/1625 ,  H01L45/1675

Abstract: A phase-changeable memory device includes a phase-changeable material pattern and first and second electrodes electrically connected to the phase-changeable material pattern. The first and second electrodes are configured to provide an electrical signal to the phase-changeable material pattern. The phase-changeable material pattern includes a first phase-changeable material layer and a second phase-changeable material layer. The first and second phase-changeable material patterns have different chemical, physical, and/or electrical characteristics. For example, the second phase-changeable material layer may have a greater resistivity than the first phase-changeable material layer. For instance, the first phase-changeable material layer may include nitrogen at a first concentration, and the second phase-changeable material layer may include nitrogen at a second concentration that is greater than the first concentration. Related devices and fabrication methods are also discussed.

Abstract translation: 可变相存储器件包括相变材料图案，以及电连接到相变材料图案的第一和第二电极。 第一和第二电极被配置为向相变材料图案提供电信号。 相变材料图案包括第一相变材料层和第二相变材料层。 第一和第二可相变材料图案具有不同的化学，物理和/或电特性。 例如，第二相变材料层可以具有比第一相变材料层更大的电阻率。 例如，第一相变材料层可以包括第一浓度的氮，第二相变材料层可以包括大于第一浓度的第二浓度的氮。 还讨论了相关设备和制造方法。

公开(公告)号：US07352021B2

公开(公告)日：2008-04-01

申请号：US10888964

申请日：2004-07-09

Applicant: Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  In-Gyu Baek ,  Young-Ki Ha

Inventor： Jun-Soo Bae ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  In-Gyu Baek ,  Young-Ki Ha

IPC: H01L29/76

CPC classification number: B82Y25/00 ,  B82Y10/00 ,  G11B5/3909 ,  G11C11/16 ,  H01F10/3254 ,  H01F41/302 ,  H01L43/08 ,  H01L43/12

Abstract: Magnetic Random Access Memory (MRAM) devices include a lower electrode and a magnetic tunnel junction on the lower electrode. The magnetic tunnel junction includes a seed layer and a tunneling barrier that is oriented in a same direction as the most closely packed plane direction of the seed layer. An oxide layer may be provided between the lower electrode and the magnetic tunnel junction. The lower electrode may be a titanium-rich TiN layer having more than 50 atomic percent titanium content. Analogous fabrication methods are also described.

Abstract translation: 磁性随机存取存储器（MRAM）器件包括下电极和下电极上的磁隧道结。 磁性隧道结包括种子层和隧道势垒，其定向在与种子层的最紧密堆积的平面方向相同的方向上。 可以在下电极和磁隧道结之间提供氧化物层。 下电极可以是具有超过50原子％钛含量的富钛TiN层。 还描述了类似的制造方法。

公开(公告)号：US20060174473A1

公开(公告)日：2006-08-10

申请号：US11347280

申请日：2006-02-06

Applicant: Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

Inventor： Se-Chung Oh ,  Jang-Eun Lee ,  Jun-Soo Bae ,  Hyun-Jo Kim ,  Kyung-Tae Nam ,  Young-Ki Ha

IPC: G11B5/33 ,  G11B5/127 ,  H04R31/00

CPC classification number: G11C11/16 ,  B82Y10/00 ,  B82Y25/00 ,  G11B5/3909 ,  H01L27/228 ,  H01L43/08 ,  H01L43/12 ,  Y10T29/49034 ,  Y10T29/49044

Abstract: Example embodiments of the present invention disclose a semiconductor memory device and a method of forming a memory device. A semiconductor memory device may include a digit line disposed on a substrate, an intermediate insulating layer covering the digit line, a magnetic tunnel junction (MTJ) pattern disposed on the intermediate insulating layer and over the digit line, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., and a bit line connected to the capping pattern and disposed to intersect the digit line. A method of forming a semiconductor memory device may include forming a digit line on a substrate, forming an intermediate insulating layer covering the digit line, forming a magnetic tunnel junction (MTJ) pattern on the intermediate insulating layer, the MTJ pattern including a sequentially stacked lower magnetic pattern, upper magnetic pattern, and capping pattern, wherein the capping pattern does not react with the upper magnetic pattern at a temperature above about 280° C., performing an annealing operation at a temperature of about 350° C. or higher, and forming a bit line connected to the capping pattern and disposed to intersect the digit line.

Abstract translation: 本发明的示例性实施例公开了半导体存储器件和形成存储器件的方法。 半导体存储器件可以包括设置在衬底上的数字线，覆盖数字线的中间绝缘层，设置在中间绝缘层上方和数字线上的磁性隧道结（MTJ）图案，MTJ图案包括顺序堆叠 下磁性图案，上磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上磁性图案反应，而位线连接到封盖图案并且设置成与数字线相交 。 形成半导体存储器件的方法可以包括在衬底上形成数字线，形成覆盖数字线的中间绝缘层，在中间绝缘层上形成磁隧道结（MTJ）图案，MTJ图案包括顺序层叠的 较低的磁性图案，上部磁性图案和封盖图案，其中封盖图案在高于约280℃的温度下不与上部磁性图案反应，在约350℃或更高的温度下进行退火操作， 并且形成连接到所述封盖图案并且设置成与所述数字线相交的位线。

公开(公告)号：US20050035383A1

公开(公告)日：2005-02-17

申请号：US10851387

申请日：2004-05-24

Applicant: Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Jun-Soo Bae ,  In-Gyu Baek ,  Se-Chung Oh

Inventor： Young-Ki Ha ,  Jang-Eun Lee ,  Hyun-Jo Kim ,  Jun-Soo Bae ,  In-Gyu Baek ,  Se-Chung Oh

IPC: G11C11/15 ,  H01F10/32 ,  H01L43/08 ,  H01L29/76

CPC classification number: B82Y25/00 ,  G11C11/15 ,  H01F10/3204 ,  H01F10/3254 ,  H01F10/3272 ,  H01F10/3295 ,  H01L43/08

Abstract: A magnetic tunnel junction device includes a magnetically programmable free magnetic layer. The free magnetic layer includes a lamination of at least two ferromagnetic layers and at least one intermediate layer interposed between the at least two ferromagnetic layers.

Abstract translation: 磁性隧道结装置包括可磁性可编程的自由磁性层。 自由磁性层包括至少两个铁磁层和至少一个介于至少两个铁磁层之间的中间层的叠层。