公开(公告)号：US20140211839A1

公开(公告)日：2014-07-31

申请号：US14228913

申请日：2014-03-28

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Pervez M. Aziz ,  Ye Liu

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L7/10 ,  H04L25/03063 ,  H04L27/0002 ,  H04L2025/03636

Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Abstract translation: 一种具有线性路径和非线性路径的接收机的通信系统。 随着接收机接收数据信号，它自适应地均衡接收信号，并且使用可饱和放大器限幅器等对非线性路径中的均衡信号进行幅度限幅。 限幅器从有限的均衡接收信号中提取数据。 在线性路径中，时钟恢复电路从均衡的接收信号产生时钟信号。 线性路径中的延迟电路至少部分地补偿限幅器中的传播延迟。 在非线性路径之外发生时钟恢复，产生低抖动时钟。 限幅器通过增加受限信号的上升和下降时间来增强数据眼睛的垂直开度，为切片机操作提供更多的噪声容限以及更大的定时裕度来采样分片数据。

公开(公告)号：US09325546B1

公开(公告)日：2016-04-26

申请号：US14541345

申请日：2014-11-14

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Brett D. Hardy

IPC: H04L27/01 ,  H04L7/00

CPC classification number: H04L7/0079 ,  H03G3/3078 ,  H04L25/0298 ,  H04L25/03878

Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts data path gain through programmable-bias based on process, voltage, temperature (PVT) and data rate changes. Such adaptation process extends bias current dynamic range, and low frequency gain can be programmed to a desired target range of values for a given variable gain amplifier (VGA) setting at any PVT and data rate corner. A receive (RX) data path structure auto-adapts data path gain through programmable bias based on sensed PVT and data rate changes. The low frequency attenuation/gain range is extended, and can be programmed to a desirable targeted range by a SerDes device RX adaptive process for a given VGA and linear equalizer (LEQ) setting at any given PVT and data rate condition.

Abstract translation: 描述的实施例在SerDes设备中提供了一种通过基于过程，电压，温度（PVT）和数据速率变化的可编程偏置来调整数据路径增益的自适应过程。 这种适应过程扩展了偏置电流动态范围，低频增益可编程为任何PVT和数据速率角下的给定可变增益放大器（VGA）设置的期望目标值范围。 接收（RX）数据路径结构通过基于感测的PVT和数据速率变化的可编程偏置来自适应数据路径增益。 低频衰减/增益范围扩展，并且可以通过在任何给定的PVT和数据速率条件下的给定VGA和线性均衡器（LEQ）设置的SerDes设备RX自适应处理来编程到期望的目标范围。

公开(公告)号：US20160072650A1

公开(公告)日：2016-03-10

申请号：US14479278

申请日：2014-09-06

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Sunil Srinivasa ,  Vladimir Sindalovsky ,  Amaresh V. Malipatil ,  Pervez M. Aziz

IPC: H04L25/06 ,  H04L7/00

CPC classification number: H04L25/06 ,  H04L7/0025 ,  H04L7/0087 ,  H04L7/033 ,  H04L25/0278 ,  H04L25/0292

Abstract: Described embodiments provide for, in a SerDes device, an adaptation process that adjusts termination impedance automatically to obtain a tuned termination. The termination adaptation is realized with a ‘biased’ bang-bang phase detector (BBPD) that biases the weights applied to UP and DOWN outputs of the phase detector. Through an optimization process, the system locks to data eye corners, and thereby is able to optimize termination though a predetermined criteria, such as signal to noise ratio (SNR), horizontal eye (H-) margin, vertical eye (V-) margin or joint SNR and H-/V-margin optimization. As part of the receiver equalization, adaptive termination tuning is performed after the SerDes receiver (RX) path is initially powered-up by tuning the termination above and below its current initial setting and performing the optimization process.

Abstract translation: 描述的实施例在SerDes设备中提供自适应调整终止阻抗以获得调谐终端的适配过程。 终端适配通过偏置的砰 - 相位相位检测器（BBPD）来实现，该相位检测器偏置施加到相位检测器的UP和DOWN输出的权重。 通过优化过程，系统锁定到数据眼角，从而能够通过诸如信噪比（SNR），水平眼（H）边缘，垂直眼（V-）边缘等预定标准来优化终止 或联合SNR和H / V边缘优化。 作为接收机均衡的一部分，在SerDes接收机（RX）路径最初上电之后，通过调谐高于和低于其当前初始设置的终止并执行优化过程来执行自适应终止调谐。

公开(公告)号：US20140233619A1

公开(公告)日：2014-08-21

申请号：US13768220

申请日：2013-02-15

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H04L27/01

CPC classification number: H04L27/01 ,  H04L1/201 ,  H04L1/205

Abstract: In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time decision feedback equalization (DFE) is employed.

Abstract translation: 在所描述的实施例中，对串行器/解串器（SerDes）器件的接收路径采用基于数据模式的信号丢失检测（LOS）。 基于模式的LOS检测允许通过各种类型的连接介质检测数据丢失，并且通常对信号衰减不敏感。 更具体地，当采用谨慎的时间判定反馈均衡（DFE）时，一些所描述的实施例公开了用于输入接收数据的不同连接介质上的LOS的可靠的基于模式的检测。

公开(公告)号：US09294314B2

公开(公告)日：2016-03-22

申请号：US14228913

申请日：2014-03-28

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Pervez M. Aziz ,  Ye Liu

IPC: H03H7/30 ,  H03H7/40 ,  H03K5/159 ,  H04L25/03 ,  H04L7/10 ,  H04L27/00

CPC classification number: H04L25/03057 ,  H04L7/10 ,  H04L25/03063 ,  H04L27/0002 ,  H04L2025/03636

Abstract: A communication system having a receiver with a linear path and a nonlinear path. As the receiver receives a data signal, it adaptively equalizes the received signal, and amplitude-limits the equalized signal in the nonlinear path using a saturable amplifier limiter or the like. A slicer extracts data from the limited equalized received signal. In the linear path, a clock recovery circuit generates a clock signal from the equalized received signal. A delay circuit in the linear path at least partially compensates for propagation delay in the limiter. Having the clock recovery occur in other than the nonlinear path, a low jitter clock is generated. The limiter enhances the vertical opening of the data eye by increasing the rise and fall times of the limited signal, providing more noise margin for the slicer to operate with and a greater timing margin in which to sample the sliced data.

Abstract translation: 一种具有线性路径和非线性路径的接收机的通信系统。 随着接收机接收数据信号，它自适应地均衡接收信号，并且使用可饱和放大器限幅器等对非线性路径中的均衡信号进行幅度限幅。 限幅器从有限的均衡接收信号中提取数据。 在线性路径中，时钟恢复电路从均衡的接收信号产生时钟信号。 线性路径中的延迟电路至少部分地补偿限幅器中的传播延迟。 在非线性路径之外发生时钟恢复，产生低抖动时钟。 限幅器通过增加受限信号的上升和下降时间来增强数据眼睛的垂直开度，为切片机操作提供更多的噪声容限，并在其中对切片数据进行采样提供更大的定时余量。

公开(公告)号：US20150249555A1

公开(公告)日：2015-09-03

申请号：US14244474

申请日：2014-04-03

Applicant: LSI Corporation

Inventor： Mohammad S. Mobin ,  Weiwei Mao ,  Chintan M. Desai ,  Freeman Y. Zhong ,  Ye Liu

IPC: H04L25/03 ,  H04L25/06

CPC classification number: H04L25/03057 ,  H04L25/03885 ,  H04L25/06

Abstract: In described embodiments, process, voltage, temperature (PVT) compensation in a serializer/deserializer (SerDes) device employs a closed loop adaptation compensation that is incorporated into the SerDes receiver adaptation process. A detection method, where the adapted decision feedback equalizer (DFE) target level (e.g., tap H0) is monitored, employs this DFE target level when implementing a closed loop variable gain amplifier adaptation. The DFE target level in conjunction with the VGA level is used to control the PVT setting to maintain target SerDes data path gain by detecting aPVT corner condition. The detected PVT corner condition is employed to generate a control signal to further adjust the LEQ and DFE data path differential pair gain as required by the PVT condition.

Abstract translation: 在所描述的实施例中，串行器/解串器（SerDes）器件中的处理，电压，温度（PVT）补偿采用并入SerDes接收器适配过程的闭环适配补偿。 在实施闭环可变增益放大器适配时，其中监视适应的判决反馈均衡器（DFE）目标电平（例如，抽头H0）的检测方法采用该DFE目标电平。 DFE目标水平与VGA电平一起用于控制PVT设置，以通过检测一个电压转角条件来维持目标SerDes数据通路增益。 检测到的PVT拐角条件用于产生控制信号，以进一步调整根据PVT条件所要求的LEQ和DFE数据路径差分对增益。

公开(公告)号：US20150110165A1

公开(公告)日：2015-04-23

申请号：US14072895

申请日：2013-11-06

Applicant: LSI Corporation

Inventor： Rajesh Ramadoss ,  Mohammad S. Mobin ,  Thomas F. Gibbons

IPC: H04L25/03

CPC classification number: H04L25/03885 ,  H04L25/03057 ,  H04L25/03343

Abstract: A method of adjusting a post-cursor tap weight in a transmitter FIR filter in a high-speed digital data transmission system. A receiver, over a forward channel, receives a signal from the transmitter and equalizes the received signal using an adaptive analog equalizer coupled to the forward channel and a decision feedback equalizer (DFE) coupled to the analog equalizer. A gain coefficient used to adjust the peaking by the analog equalizer is adapted using an error signal generated by the DFE. The post-cursor tap weight of the transmitter filter is adjusted up or down based on a comparison of the gain coefficient to a set. of limits. The post-cursor tap weight is transmitted to the transmitter over a reverse channel and then equalizers in the receiver readapt. Alternatively, eye opening data and a DFE tap coefficient are used to determine whether the post-cursor tap weight is adjusted up or down.

Abstract translation: 一种在高速数字数据传输系统中调整发射机FIR滤波器中的后光标抽头权重的方法。 接收机通过前向信道接收来自发射机的信号，并使用耦合到前向信道的自适应模拟均衡器和耦合到模拟均衡器的判决反馈均衡器（DFE）来均衡接收信号。 用于通过模拟均衡器调节峰值的增益系数使用DFE产生的误差信号进行调整。 基于增益系数与一组的比较，发送器滤波器的后置光标重量被上下调整。 的限制。 后置光标抽头权重通过反向通道发送到发送器，然后在接收器中对其进行均衡。 或者，使用眼睛打开数据和DFE抽头系数来确定是否向上或向下调整后光标抽头重量。

公开(公告)号：US08953665B2

公开(公告)日：2015-02-10

申请号：US13768220

申请日：2013-02-15

Applicant: LSI Corporation

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H04L27/01 ,  H04L1/20

CPC classification number: H04L27/01 ,  H04L1/201 ,  H04L1/205

Abstract: In described embodiments, data pattern-based detection of loss of signal (LOS) is employed for a receive path of serializer/deserializer (SerDes) devices. Pattern-based LOS detection allows for detection of data loss over variety of types of connection media, and is generally insensitive to signal attenuation. More specifically, some described embodiments disclose reliable pattern-based detection of LOS across different connection media for incoming receive data when discreet time decision feedback equalization (DFE) is employed.

Abstract translation: 在所描述的实施例中，对串行器/解串器（SerDes）器件的接收路径采用基于数据模式的信号丢失检测（LOS）。 基于模式的LOS检测允许通过各种类型的连接介质检测数据丢失，并且通常对信号衰减不敏感。 更具体地，当采用谨慎的时间判定反馈均衡（DFE）时，一些所描述的实施例公开了用于输入接收数据的不同连接介质上的LOS的可靠的基于模式的检测。

公开(公告)号：US20140132320A1

公开(公告)日：2014-05-15

申请号：US13675520

申请日：2012-11-13

Applicant: LSI CORPORATION

Inventor： Vladimir Sindalovsky ,  Mohammad S. Mobin ,  Lane A. Smith

IPC: H03L7/087

CPC classification number: H03L7/087 ,  H03L7/0807 ,  H03L7/095 ,  H04L7/0083 ,  H04L7/033 ,  Y10S331/02

Abstract: An apparatus comprises a clock and data recovery system, and a loss of lock detector at least partially incorporated within or otherwise associated with the clock and data recovery system. The loss of lock detector is configured to generate a loss of lock signal responsive to phase adjustment requests generated for a clock signal in the clock and data recovery system. By way of example, the loss of lock signal may have a first logic level indicative of the phase adjustment requests occurring at a first rate associated with a lock condition and a second logic level indicative of the phase adjustment requests occurring at a second rate lower than the first rate. Absolute values of respective phase increments each associated with multiple up and down phase requests may be accumulated, and the loss of lock signal generated as a function of the accumulated phase increment absolute values.

Abstract translation: 一种装置包括时钟和数据恢复系统，以及至少部分地并入或与时钟和数据恢复系统相关联的锁定检测器的丢失。 锁定检测器的丢失被配置为响应于针对时钟和数据恢复系统中的时钟信号产生的相位调整请求产生锁定信号的丢失。 作为示例，锁定信号的丢失可以具有指示以与锁定状态相关联的第一速率发生的相位调整请求的第一逻辑电平，以及指示以低于第二速率的第二速率发生的相位调整请求的第二逻辑电平 第一率。 可以累积与多个上升和下降相位请求相关联的各个相位增量的绝对值，并且作为积累的相位增量绝对值的函数产生的锁定信号的丢失。