公开(公告)号：US20110049645A1

公开(公告)日：2011-03-03

申请号：US12550543

申请日：2009-08-31

申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey Sleight

IPC分类号： H01L29/78 ,  H01L21/28

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966

摘要： A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack.

摘要翻译： 一种结构包括衬底和设置在衬底上的栅叠层。 该结构还包括设置在栅极堆叠的侧壁上并已经暴露于等离子体源的氮化物封装层。 该结构还包括在氮化物封装层与栅叠层的侧壁接触的区域中与氮化物封装层接触的至少一个其它元件。

公开(公告)号：US08247877B2

公开(公告)日：2012-08-21

申请号：US12550543

申请日：2009-08-31

申请人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Renee T. Mo ,  Jeffrey Sleight

IPC分类号： H01L29/78

CPC分类号： H01L29/4983 ,  H01L21/28247 ,  H01L29/495 ,  H01L29/4966

摘要： A structure includes a substrate and a gate stack disposed on the substrate. The structure also includes a nitride encapsulation layer disposed on a side wall of the gate stack and which has been exposed to a plasma source. The structure also includes at least one other element contacting the nitride encapsulation layer in a region where the nitride encapsulation layer contacts the side wall of the gate stack.

摘要翻译： 一种结构包括衬底和设置在衬底上的栅叠层。 该结构还包括设置在栅极堆叠的侧壁上并已经暴露于等离子体源的氮化物封装层。 该结构还包括在氮化物封装层接触栅叠层的侧壁的区域中与氮化物封装层接触的至少一个其它元件。

公开(公告)号：US08536041B2

公开(公告)日：2013-09-17

申请号：US13559182

申请日：2012-07-26

申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L29/78 ,  H01L27/01

CPC分类号： H01L21/84 ,  H01L21/823412 ,  H01L21/823462 ,  H01L21/823468 ,  H01L21/823807 ,  H01L21/823857 ,  H01L21/823864 ,  H01L27/1203 ,  H01L29/4958 ,  H01L29/517 ,  H01L29/66772 ,  H01L29/78654

摘要： A method is provided for fabricating a transistor. The transistor includes a silicon layer including a source region and a drain region, a gate stack disposed on the silicon layer between the source region and the drain region, and a sidewall spacer disposed on sidewalls of the gate stack. The gate stack includes a first layer of high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. The sidewall spacer includes a high dielectric constant material and covers the sidewalls of at least the second and third layers of the gate stack. Also provided is a method for fabricating such a transistor.

摘要翻译： 提供了一种用于制造晶体管的方法。 该晶体管包括一个硅层，该硅层包括一个源区和一个漏极区，一个位于源极区和漏极区之间的硅层上的栅极堆叠，以及设置在栅叠层的侧壁上的侧壁隔离层。 栅堆叠包括第一层高介电常数材料，第二层包括金属或金属合金，以及第三层包括硅或多晶硅。 侧壁间隔件包括高介电常数材料并且覆盖至少栅极叠层的第二和第三层的侧壁。 还提供了制造这种晶体管的方法。

公开(公告)号：US20130176771A1

公开(公告)日：2013-07-11

申请号：US13345636

申请日：2012-01-06

申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC分类号： G11C11/40

CPC分类号： G11C16/24 ,  G11C11/412 ,  H01L27/0207 ,  H01L27/1104 ,  H01L27/1116

摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line through a series outer diode between the pass-gate and the write bit line oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

摘要翻译： 一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到通过栅极和写入位之间的串联外部二极管的写入位线的每个通过栅极晶体管的源极或漏极 线路阻止从写入位线进入电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。

公开(公告)号：US08159028B2

公开(公告)日：2012-04-17

申请号：US12543692

申请日：2009-08-19

申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L29/72

CPC分类号： H01L29/4908 ,  H01L21/28114 ,  H01L29/42384 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.

公开(公告)号：US20090275182A1

公开(公告)日：2009-11-05

申请号：US12113557

申请日：2008-05-01

申请人： LELAND CHANG ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： LELAND CHANG ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L21/336

CPC分类号： H01L29/4958 ,  H01L21/28114 ,  H01L29/42376 ,  H01L29/517 ,  H01L29/6653 ,  H01L29/6659 ,  H01L29/7833

摘要： A method is provided for fabricating a transistor. A silicon layer is provided, and a first layer comprising a high dielectric constant material is formed on the silicon layer. A second layer including a metal or metal alloy is formed on the first layer, and a third layer including silicon or polysilicon is formed on the second layer. The first, second, and third layers are etched so as to form a gate stack, and ions are implanted to form source and drain regions in the silicon layer. Source and drain silicide contact areas are formed in the source and drain regions, and a gate silicide contact area is formed in the third layer. After forming these silicide contact areas, the third layer is etched without etching the first and second layers, so as to substantially reduce the width of the third layer.

摘要翻译： 提供了一种用于制造晶体管的方法。 提供硅层，在硅层上形成包含高介电常数材料的第一层。 在第一层上形成包括金属或金属合金的第二层，并且在第二层上形成包括硅或多晶硅的第三层。 蚀刻第一层，第二层和第三层以便形成栅叠层，并注入离子以在硅层中形成源区和漏区。 源极和漏极硅化物接触区域形成在源极和漏极区域中，并且在第三层中形成栅极硅化物接触区域。 在形成这些硅化物接触区域之后，蚀刻第三层而不蚀刻第一层和第二层，从而基本上减小第三层的宽度。

公开(公告)号：US20130176769A1

公开(公告)日：2013-07-11

申请号：US13345619

申请日：2012-01-06

申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC分类号： G11C11/40

CPC分类号： G11C11/417 ,  G11C11/412

摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration to form two inverters for storing a single data bit, wherein each of the inverters includes a Schottky diode; first and second pass gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass gate transistors coupled to a write bit line; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. In a preferred embodiment, the 8-transistor SRAM cell has column select writing enabled for writing a value to the 8-transistor SRAM cell without inadvertently also writing a value to another 8-transistor SRAM cell.

摘要翻译： 一种8晶体管SRAM单元，其包括两个上拉晶体管和两个交叉耦合的反相器配置的下拉晶体管，以形成用于存储单个数据位的两个反相器，其中每个反相器包括肖特基二极管; 第一和第二栅极晶体管，其具有耦合到写入字线的栅极端子和耦合到写位线的每个通路栅极晶体管的源极或漏极; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 在优选实施例中，8晶体管SRAM单元具有使能用于向8晶体管SRAM单元写入值的列选择写入，而无需另外向另一个8-晶体管SRAM单元写入一个值。

公开(公告)号：US07736981B2

公开(公告)日：2010-06-15

申请号：US12113527

申请日：2008-05-01

申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L29/72

CPC分类号： H01L29/4908 ,  H01L21/28114 ,  H01L29/42384 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66772 ,  H01L29/7833

摘要： A transistor is provided. The transistor includes a silicon layer including a source region and a drain region. A gate stack is disposed on the silicon layer between the source region and the drain region. The gate stack comprises a first layer of a high dielectric constant material, a second layer comprising a metal or metal alloy, and a third layer comprising silicon or polysilicon. A lateral extent of the second layer of the gate stack is substantially greater than a lateral extent of the third layer of the gate stack. Also provided are methods for fabricating such a transistor.

摘要翻译： 提供晶体管。 晶体管包括包含源极区和漏极区的硅层。 栅极堆叠设置在源极区域和漏极区域之间的硅层上。 栅堆叠包括高介电常数材料的第一层，包含金属或金属合金的第二层，以及包含硅或多晶硅的第三层。 栅极堆叠的第二层的横向范围基本上大于栅极堆叠的第三层的横向范围。 还提供了制造这种晶体管的方法。

公开(公告)号：US20100032759A1

公开(公告)日：2010-02-11

申请号：US12189639

申请日：2008-08-11

申请人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Jeffrey W. Sleight

IPC分类号： H01L21/336 ,  H01L29/786

CPC分类号： H01L29/78612 ,  H01L29/66772

摘要： A self-aligned Silicon on Insulator (SOI) Schottky Body Tie structure includes: a source region comprising a silicide layer disposed on a top surface of the source region; a drain region comprising a silicide layer disposed on a top surface of the drain region; a gate region disposed above a channel formed by the drain and source regions; and a gate oxide layer disposed between the gate region and the channel formed by the drain and source regions, wherein when silicidation is performed on the diffusion region it forms a metal-silicon alloy contact such that the silicide layer extends into and directly touches the channel.

摘要翻译： 自对准硅绝缘体（SOI）肖特基体系结构包括：源极区，包括设置在源极区的顶表面上的硅化物层; 漏极区，包括设置在所述漏极区的顶表面上的硅化物层; 栅极区域，设置在由漏极和源极区域形成的沟道上方; 以及栅极氧化物层，其设置在由漏极和源极区域形成的栅极区域和沟道之间，其中当对扩散区域进行硅化时，其形成金属 - 硅合金接触，使得硅化物层延伸到沟道中并直接接触沟道 。

公开(公告)号：US08619465B2

公开(公告)日：2013-12-31

申请号：US13345629

申请日：2012-01-06

申请人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

发明人： Leland Chang ,  Isaac Lauer ,  Chung-Hsun Lin ,  Jeffrey W. Sleight

IPC分类号： G11C11/00 ,  G11C11/412

CPC分类号： G11C11/412

摘要： An 8-transistor SRAM cell which includes two pull-up transistors and two pull-down transistors in cross-coupled inverter configuration for storing a single data bit; first and second pass-gate transistors having a gate terminal coupled to a write word line and a source or drain of each of the pass-gate transistors coupled to a write bit line; inner junction diodes at shared source/drain terminals of the pass-gate and pull-down transistors oriented to block charge transfer from the write bit line into the cell; and first and second read transistors coupled to the two pull-up and two pull-down transistors, one of the read transistors having a gate terminal coupled to a read word line and a source or a drain coupled to a read bit line. The 8-transistor SRAM cell is adapted to prevent the value of the bit stored in the cell from changing state.

摘要翻译： 一个8晶体管SRAM单元，包括两个上拉晶体管和两个交叉耦合的反相器配置中的下拉晶体管，用于存储单个数据位; 第一和第二栅极晶体管具有耦合到写入字线的栅极端子和耦合到写入位线的每个通过栅极晶体管的源极或漏极; 导通栅极和下拉晶体管的共用源极/漏极端子处的内部结二极管，用于阻止从写位线到电池的电荷转移; 以及耦合到所述两个上拉和两个下拉晶体管的第一和第二读取晶体管，所述读取晶体管中的一个具有耦合到读取字线的栅极端子和耦合到读取位线的源极或漏极。 8晶体管SRAM单元适于防止存储在单元中的位的值改变状态。