公开(公告)号：US20240290722A1

公开(公告)日：2024-08-29

申请号：US18652551

申请日：2024-05-01

Applicant: Lodestar Licensing Group LLC

Inventor： Jordan D. Greenlee ,  Lifang Xu ,  Rita J. Klein ,  Xiao Li ,  Everett A. McTeer

IPC: H01L23/532 ,  H01L21/768 ,  H01L23/00 ,  H01L23/522 ,  H10B41/27 ,  H10B41/41

CPC classification number: H01L23/53266 ,  H01L21/76846 ,  H01L23/5226 ,  H01L23/562 ,  H10B41/27 ,  H10B41/41

Abstract: An apparatus comprising at least one contact structure. The at least one contact structure comprises a contact, an insulating material overlying the contact, and at least one contact via in the insulating material. The at least one contact structure also comprises a dielectric liner material adjacent the insulating material within the contact via, a conductive material adjacent the dielectric liner material, and a stress compensation material adjacent the conductive material and in a central portion of the at least one contact via. The stress compensation material is at least partially surrounded by the conductive material. Memory devices, electronic systems, and methods of forming the apparatus are also disclosed.

公开(公告)号：US12063782B2

公开(公告)日：2024-08-13

申请号：US17941900

申请日：2022-09-09

Applicant: Lodestar Licensing Group LLC

Inventor： John D. Hopkins ,  Justin D. Shepherdson ,  Collin Howder ,  Jordan D. Greenlee

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/28 ,  H01L21/285 ,  H01L21/311 ,  H01L29/66 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

CPC classification number: H10B43/27 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/28518 ,  H01L21/31111 ,  H01L29/40114 ,  H01L29/40117 ,  H01L29/66545 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: Some embodiments include methods of forming integrated assemblies. A conductive structure is formed to include a semiconductor-containing material over a metal-containing material. An opening is formed to extend into the conductive structure. A conductive material is formed along a bottom of the opening. A stack of alternating first and second materials is formed over the conductive structure either before or after forming the conductive material. Insulative material and/or channel material is formed to extend through the stack to contact the conductive material. Some embodiments include integrated assemblies.

公开(公告)号：US20250056800A1

公开(公告)日：2025-02-13

申请号：US18828721

申请日：2024-09-09

Applicant: Lodestar Licensing Group LLC

Inventor： Jordan D. Greenlee ,  Daniel Billingsley ,  Indra V. Chary ,  Rita J. Klein

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/311 ,  H01L29/66 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.

公开(公告)号：US12096633B2

公开(公告)日：2024-09-17

申请号：US17517459

申请日：2021-11-02

Applicant: Lodestar Licensing Group LLC

Inventor： Jordan D. Greenlee ,  Daniel Billingsley ,  Indra V. Chary ,  Rita J. Klein

IPC: H10B43/27 ,  H01L21/02 ,  H01L21/311 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L29/66

CPC classification number: H10B43/27 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/02636 ,  H01L21/31111 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H01L29/66545

Abstract: A memory array comprising strings of memory cells comprises laterally-spaced memory blocks individually comprising a vertical stack comprising alternating insulative tiers and conductive tiers. Operative channel-material strings of memory cells extend through the insulative tiers and the conductive tiers. Upper masses comprise first material laterally-between and longitudinally-spaced-along immediately-laterally-adjacent of the memory blocks and second material laterally-between and longitudinally-spaced-along the immediately-laterally-adjacent memory blocks longitudinally-between and under the upper masses. The second material is of different composition from that of the first material. The second material comprises insulative material. Other embodiments, including method, are disclosed.

公开(公告)号：US11990528B2

公开(公告)日：2024-05-21

申请号：US18083428

申请日：2022-12-16

Applicant: Lodestar Licensing Group LLC

Inventor： David Ross Economy ,  Rita J. Klein ,  Jordan D. Greenlee ,  John Mark Meldrim ,  Brenda D. Kraus ,  Everett A. McTeer

IPC: H01L29/49 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

CPC classification number: H01L29/4966 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B41/35 ,  H10B43/35

Abstract: Some embodiments include a memory array having a vertical stack of alternating insulative levels and control gate levels. Channel material extends vertically along the stack. The control gate levels comprising conductive regions. The conductive regions include at least three different materials. Charge-storage regions are adjacent the control gate levels. Charge-blocking regions are between the charge-storage regions and the conductive regions.