公开(公告)号：US20110219208A1

公开(公告)日：2011-09-08

申请号：US13004007

申请日：2011-01-10

申请人： Sameh Asaad ,  Ralph E. Bellofatto ,  Michael A. Blocksome ,  Matthias A. Blumrich ,  Peter Boyle ,  Jose R. Brunheroto ,  Dong Chen ,  Chen-Yong Cher ,  George L. Chiu ,  Norman Christ ,  Paul W. Coteus ,  Kristan D. Davis ,  Gabor J. Dozsa ,  Alexandre E. Eichenberger ,  Noel A. Eisley ,  Matthew R. Ellavsky ,  Kahn C. Evans ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Alan Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Michael K. Gschwind ,  John A. Gunnels ,  Shawn A. Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Todd A. Inglett ,  Brant L. Knudson ,  Gerard V. Kopcsay ,  Sameer Kumar ,  Amith R. Mamidala ,  James A. Marcella ,  Mark G. Megerian ,  Douglas R. Miller ,  Samuel J. Miller ,  Adam J. Muff ,  Michael B. Mundy ,  John K. O'Brien ,  Kathryn M. O'Brien ,  Martin Ohmacht ,  Jeffrey J. Parker ,  Ruth J. Poole ,  Joseph D. Ratterman ,  Valentina Salapura ,  David L. Satterfield ,  Robert M. Senger ,  Brian Smith ,  Burkhard Steinmacher-Burow ,  William M. Stockdell ,  Craig B. Stunkel ,  Krishnan Sugavanam ,  Yutaka Sugawara ,  Todd E. Takken ,  Barry M. Trager ,  James L. Van Oosten ,  Charles D. Wait ,  Robert E. Walkup ,  Alfred T. Watson ,  Robert W. Wisniewski ,  Peng Wu

发明人： Sameh Asaad ,  Ralph E. Bellofatto ,  Michael A. Blocksome ,  Matthias A. Blumrich ,  Peter Boyle ,  Jose R. Brunheroto ,  Dong Chen ,  Chen-Yong Cher ,  George L. Chiu ,  Norman Christ ,  Paul W. Coteus ,  Kristan D. Davis ,  Gabor J. Dozsa ,  Alexandre E. Eichenberger ,  Noel A. Eisley ,  Matthew R. Ellavsky ,  Kahn C. Evans ,  Bruce M. Fleischer ,  Thomas W. Fox ,  Alan Gara ,  Mark E. Giampapa ,  Thomas M. Gooding ,  Michael K. Gschwind ,  John A. Gunnels ,  Shawn A. Hall ,  Rudolf A. Haring ,  Philip Heidelberger ,  Todd A. Inglett ,  Brant L. Knudson ,  Gerard V. Kopcsay ,  Sameer Kumar ,  Amith R. Mamidala ,  James A. Marcella ,  Mark G. Megerian ,  Douglas R. Miller ,  Samuel J. Miller ,  Adam J. Muff ,  Michael B. Mundy ,  John K. O'Brien ,  Kathryn M. O'Brien ,  Martin Ohmacht ,  Jeffrey J. Parker ,  Ruth J. Poole ,  Joseph D. Ratterman ,  Valentina Salapura ,  David L. Satterfield ,  Robert M. Senger ,  Brian Smith ,  Burkhard Steinmacher-Burow ,  William M. Stockdell ,  Craig B. Stunkel ,  Krishnan Sugavanam ,  Yutaka Sugawara ,  Todd E. Takken ,  Barry M. Trager ,  James L. Van Oosten ,  Charles D. Wait ,  Robert E. Walkup ,  Alfred T. Watson ,  Robert W. Wisniewski ,  Peng Wu

IPC分类号： G06F15/76 ,  G06F9/06

CPC分类号： G06F13/287 ,  G06F9/06 ,  G06F9/3004 ,  G06F9/30047 ,  G06F9/3885 ,  G06F12/0811 ,  G06F12/0831 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/1027 ,  G06F15/17381 ,  G06F15/17387 ,  G06F15/76 ,  G06F15/8069 ,  G06F2212/1016 ,  G06F2212/602 ,  G06F2212/6022 ,  G06F2212/6024 ,  G06F2212/6032 ,  Y02D10/13 ,  Y02D10/14

摘要： A Multi-Petascale Highly Efficient Parallel Supercomputer of 100 petaOPS-scale computing, at decreased cost, power and footprint, and that allows for a maximum packaging density of processing nodes from an interconnect point of view. The Supercomputer exploits technological advances in VLSI that enables a computing model where many processors can be integrated into a single Application Specific Integrated Circuit (ASIC). Each ASIC computing node comprises a system-on-chip ASIC utilizing four or more processors integrated into one die, with each having full access to all system resources and enabling adaptive partitioning of the processors to functions such as compute or messaging I/O on an application by application basis, and preferably, enable adaptive partitioning of functions in accordance with various algorithmic phases within an application, or if I/O or other processors are underutilized, then can participate in computation or communication nodes are interconnected by a five dimensional torus network with DMA that optimally maximize the throughput of packet communications between nodes and minimize latency.

摘要翻译： 具有100 petaOPS规模计算的多Petascale高效并行超级计算机，其成本，功耗和占地面积都在降低，并且允许从互连角度来看处理节点的最大封装密度。 超级计算机利用了VLSI的技术进步，实现了许多处理器可以集成到单个专用集成电路（ASIC）中的计算模型。 每个ASIC计算节点包括利用集成到一个管芯中的四个或更多个处理器的片上系统ASIC，每个处理器具有对所有系统资源的完全访问，并且使得处理器能够对诸如计算或消息传递I / O 并且优选地，根据应用内的各种算法阶段实现功能的自适应分割，或者如果I / O或其他处理器未被充分利用，则可以参与计算或通信节点通过五维环面网络互连 使用DMA来最大限度地最大化节点之间的分组通信的吞吐量并最小化等待时间。